From 442dd437e10dbbcc522379da9adbbbf9dca9b2f2 Mon Sep 17 00:00:00 2001 From: TSR Berry <20988865+TSRBerry@users.noreply.github.com> Date: Fri, 14 Oct 2022 17:27:47 +0200 Subject: [PATCH] aarch64: Move FPCR and FPSR registers to not break compatibility Co-authored-by: merry --- include/unicorn/arm64.h | 8 ++++---- qemu/target/arm/unicorn_aarch64.c | 24 ++++++++++++------------ 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/include/unicorn/arm64.h b/include/unicorn/arm64.h index aab2ab9c..fd8192fb 100644 --- a/include/unicorn/arm64.h +++ b/include/unicorn/arm64.h @@ -313,10 +313,6 @@ typedef enum uc_arm64_reg { UC_ARM64_REG_PSTATE, - //> floating point control and status registers - UC_ARM64_REG_FPCR, - UC_ARM64_REG_FPSR, - //> exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead UC_ARM64_REG_ELR_EL0, UC_ARM64_REG_ELR_EL1, @@ -354,6 +350,10 @@ typedef enum uc_arm64_reg { UC_ARM64_REG_CP_REG, + //> floating point control and status registers + UC_ARM64_REG_FPCR, + UC_ARM64_REG_FPSR, + UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers //> alias registers diff --git a/qemu/target/arm/unicorn_aarch64.c b/qemu/target/arm/unicorn_aarch64.c index 4b533047..fec0db68 100644 --- a/qemu/target/arm/unicorn_aarch64.c +++ b/qemu/target/arm/unicorn_aarch64.c @@ -210,12 +210,6 @@ static uc_err reg_read(CPUARMState *env, unsigned int regid, void *value) case UC_ARM64_REG_PSTATE: *(uint32_t *)value = pstate_read(env); break; - case UC_ARM64_REG_FPCR: - *(uint32_t *)value = vfp_get_fpcr(env); - break; - case UC_ARM64_REG_FPSR: - *(uint32_t *)value = vfp_get_fpsr(env); - break; case UC_ARM64_REG_TTBR0_EL1: *(uint64_t *)value = env->cp15.ttbr0_el[1]; break; @@ -231,6 +225,12 @@ static uc_err reg_read(CPUARMState *env, unsigned int regid, void *value) case UC_ARM64_REG_CP_REG: ret = read_cp_reg(env, (uc_arm64_cp_reg *)value); break; + case UC_ARM64_REG_FPCR: + *(uint32_t *)value = vfp_get_fpcr(env); + break; + case UC_ARM64_REG_FPSR: + *(uint32_t *)value = vfp_get_fpsr(env); + break; } } @@ -309,12 +309,6 @@ static uc_err reg_write(CPUARMState *env, unsigned int regid, const void *value) case UC_ARM64_REG_PSTATE: pstate_write(env, *(uint32_t *)value); break; - case UC_ARM64_REG_FPCR: - vfp_set_fpcr(env, *(uint32_t *)value); - break; - case UC_ARM64_REG_FPSR: - vfp_set_fpsr(env, *(uint32_t *)value); - break; case UC_ARM64_REG_TTBR0_EL1: env->cp15.ttbr0_el[1] = *(uint64_t *)value; break; @@ -330,6 +324,12 @@ static uc_err reg_write(CPUARMState *env, unsigned int regid, const void *value) case UC_ARM64_REG_CP_REG: ret = write_cp_reg(env, (uc_arm64_cp_reg *)value); break; + case UC_ARM64_REG_FPCR: + vfp_set_fpcr(env, *(uint32_t *)value); + break; + case UC_ARM64_REG_FPSR: + vfp_set_fpsr(env, *(uint32_t *)value); + break; } }