feat(arm): add an ESR register (#2155)

This allows users to read/write from the ARM syndrome value like in
AArch64.
This commit is contained in:
Amaan Qureshi
2025-04-12 09:46:37 -04:00
committed by GitHub
parent 7f48b1dd4a
commit 3a7bde03b8
11 changed files with 73 additions and 16 deletions

View File

@@ -185,7 +185,8 @@ const
UC_ARM_REG_XPSR_G = 137;
UC_ARM_REG_XPSR_NZCVQG = 138;
UC_ARM_REG_CP_REG = 139;
UC_ARM_REG_ENDING = 140;
UC_ARM_REG_ESR = 140;
UC_ARM_REG_ENDING = 141;
// alias registers
UC_ARM_REG_R13 = 12;
@@ -197,4 +198,4 @@ const
UC_ARM_REG_IP = 78;
implementation
end.
end.