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feat(arm): add an ESR register (#2155)

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This allows users to read/write from the ARM syndrome value like in
AArch64.
This commit is contained in:
Amaan Qureshi
2025-04-12 09:46:37 -04:00
committed by GitHub
parent 7f48b1dd4a
commit 3a7bde03b8
11 changed files with 73 additions and 16 deletions
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3
bindings/dotnet/UnicornEngine/Const/Arm.fs
View File

@@ -187,7 +187,8 @@ module Arm =
let UC_ARM_REG_XPSR_G = 137
let UC_ARM_REG_XPSR_NZCVQG = 138
let UC_ARM_REG_CP_REG = 139
let UC_ARM_REG_ENDING = 140
let UC_ARM_REG_ESR = 140
let UC_ARM_REG_ENDING = 141
// alias registers
let UC_ARM_REG_R13 = 12

5
bindings/go/unicorn/arm_const.go
View File

@@ -182,7 +182,8 @@ const (
ARM_REG_XPSR_G = 137
ARM_REG_XPSR_NZCVQG = 138
ARM_REG_CP_REG = 139
ARM_REG_ENDING = 140
ARM_REG_ESR = 140
ARM_REG_ENDING = 141
// alias registers
ARM_REG_R13 = 12
@@ -192,4 +193,4 @@ const (
ARM_REG_SL = 76
ARM_REG_FP = 77
ARM_REG_IP = 78
)
)

3
bindings/java/src/main/java/unicorn/ArmConst.java
View File

@@ -184,7 +184,8 @@ public interface ArmConst {
public static final int UC_ARM_REG_XPSR_G = 137;
public static final int UC_ARM_REG_XPSR_NZCVQG = 138;
public static final int UC_ARM_REG_CP_REG = 139;
public static final int UC_ARM_REG_ENDING = 140;
public static final int UC_ARM_REG_ESR = 140;
public static final int UC_ARM_REG_ENDING = 141;
// alias registers
public static final int UC_ARM_REG_R13 = 12;

5
bindings/pascal/unicorn/ArmConst.pas
View File

@@ -185,7 +185,8 @@ const
UC_ARM_REG_XPSR_G = 137;
UC_ARM_REG_XPSR_NZCVQG = 138;
UC_ARM_REG_CP_REG = 139;
UC_ARM_REG_ENDING = 140;
UC_ARM_REG_ESR = 140;
UC_ARM_REG_ENDING = 141;
// alias registers
UC_ARM_REG_R13 = 12;
@@ -197,4 +198,4 @@ const
UC_ARM_REG_IP = 78;
implementation
end.
end.

3
bindings/python/unicorn/arm_const.py
View File

@@ -180,7 +180,8 @@ UC_ARM_REG_XPSR_NZCVQ = 136
UC_ARM_REG_XPSR_G = 137
UC_ARM_REG_XPSR_NZCVQG = 138
UC_ARM_REG_CP_REG = 139
UC_ARM_REG_ENDING = 140
UC_ARM_REG_ESR = 140
UC_ARM_REG_ENDING = 141
# alias registers
UC_ARM_REG_R13 = 12

5
bindings/ruby/unicorn_gem/lib/unicorn_engine/arm_const.rb
View File

@@ -182,7 +182,8 @@ module UnicornEngine
UC_ARM_REG_XPSR_G = 137
UC_ARM_REG_XPSR_NZCVQG = 138
UC_ARM_REG_CP_REG = 139
UC_ARM_REG_ENDING = 140
UC_ARM_REG_ESR = 140
UC_ARM_REG_ENDING = 141
# alias registers
UC_ARM_REG_R13 = 12
@@ -192,4 +193,4 @@ module UnicornEngine
UC_ARM_REG_SL = 76
UC_ARM_REG_FP = 77
UC_ARM_REG_IP = 78
end
end

3
bindings/rust/src/arm.rs
View File

@@ -145,7 +145,8 @@ pub enum RegisterARM {
XPSR_G = 137,
XPSR_NZCVQG = 138,
CP_REG = 139,
ENDING = 140,
ESR = 140,
ENDING = 141,
}
impl RegisterARM {

3
bindings/zig/unicorn/arm_const.zig
View File

@@ -182,7 +182,8 @@ pub const armConst = enum(c_int) {
ARM_REG_XPSR_G = 137,
ARM_REG_XPSR_NZCVQG = 138,
ARM_REG_CP_REG = 139,
ARM_REG_ENDING = 140,
ARM_REG_ESR = 140,
ARM_REG_ENDING = 141,
// alias registers
ARM_REG_R13 = 12,