import
This commit is contained in:
Nguyen Anh Quynh
29
qemu/include/hw/i386/apic.h
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29
qemu/include/hw/i386/apic.h
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#ifndef APIC_H
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#define APIC_H
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#include "qemu-common.h"
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/* apic.c */
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int apic_accept_pic_intr(DeviceState *s);
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int apic_get_interrupt(DeviceState *s);
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void cpu_set_apic_base(struct uc_struct *uc, DeviceState *s, uint64_t val);
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uint64_t cpu_get_apic_base(struct uc_struct *uc, DeviceState *s);
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void cpu_set_apic_tpr(struct uc_struct *uc, DeviceState *s, uint8_t val);
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uint8_t cpu_get_apic_tpr(struct uc_struct *uc, DeviceState *s);
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void apic_init_reset(struct uc_struct *uc, DeviceState *s);
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void apic_sipi(DeviceState *s);
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void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
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TPRAccess access);
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void apic_poll_irq(DeviceState *d);
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void apic_designate_bsp(struct uc_struct *uc, DeviceState *d);
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/* pc.c */
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DeviceState *cpu_get_current_apic(struct uc_struct *uc);
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/* cpu.c */
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bool cpu_is_bsp(X86CPU *cpu);
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void apic_register_types(struct uc_struct *uc);
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void apic_common_register_types(struct uc_struct *uc);
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#endif
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147
qemu/include/hw/i386/apic_internal.h
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147
qemu/include/hw/i386/apic_internal.h
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/*
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* APIC support - internal interfaces
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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* Copyright (c) 2011 Jan Kiszka, Siemens AG
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#ifndef QEMU_APIC_INTERNAL_H
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#define QEMU_APIC_INTERNAL_H
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#include "exec/memory.h"
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#include "hw/cpu/icc_bus.h"
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#include "qemu/timer.h"
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/* APIC Local Vector Table */
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#define APIC_LVT_TIMER 0
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#define APIC_LVT_THERMAL 1
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#define APIC_LVT_PERFORM 2
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#define APIC_LVT_LINT0 3
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#define APIC_LVT_LINT1 4
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#define APIC_LVT_ERROR 5
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#define APIC_LVT_NB 6
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/* APIC delivery modes */
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#define APIC_DM_FIXED 0
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#define APIC_DM_LOWPRI 1
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#define APIC_DM_SMI 2
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#define APIC_DM_NMI 4
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#define APIC_DM_INIT 5
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#define APIC_DM_SIPI 6
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#define APIC_DM_EXTINT 7
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/* APIC destination mode */
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#define APIC_DESTMODE_FLAT 0xf
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#define APIC_DESTMODE_CLUSTER 1
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#define APIC_TRIGGER_EDGE 0
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#define APIC_TRIGGER_LEVEL 1
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#define APIC_LVT_TIMER_PERIODIC (1<<17)
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#define APIC_LVT_MASKED (1<<16)
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#define APIC_LVT_LEVEL_TRIGGER (1<<15)
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#define APIC_LVT_REMOTE_IRR (1<<14)
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#define APIC_INPUT_POLARITY (1<<13)
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#define APIC_SEND_PENDING (1<<12)
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#define ESR_ILLEGAL_ADDRESS (1 << 7)
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#define APIC_SV_DIRECTED_IO (1<<12)
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#define APIC_SV_ENABLE (1<<8)
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#define VAPIC_ENABLE_BIT 0
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#define VAPIC_ENABLE_MASK (1 << VAPIC_ENABLE_BIT)
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#define MAX_APICS 255
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typedef struct APICCommonState APICCommonState;
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#define TYPE_APIC_COMMON "apic-common"
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#define APIC_COMMON(uc, obj) \
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OBJECT_CHECK(uc, APICCommonState, (obj), TYPE_APIC_COMMON)
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#define APIC_COMMON_CLASS(uc, klass) \
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OBJECT_CLASS_CHECK(uc, APICCommonClass, (klass), TYPE_APIC_COMMON)
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#define APIC_COMMON_GET_CLASS(uc, obj) \
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OBJECT_GET_CLASS(uc, APICCommonClass, (obj), TYPE_APIC_COMMON)
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typedef struct APICCommonClass
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{
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ICCDeviceClass parent_class;
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DeviceRealize realize;
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void (*set_base)(APICCommonState *s, uint64_t val);
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void (*set_tpr)(APICCommonState *s, uint8_t val);
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uint8_t (*get_tpr)(APICCommonState *s);
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void (*enable_tpr_reporting)(APICCommonState *s, bool enable);
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void (*vapic_base_update)(APICCommonState *s);
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void (*external_nmi)(APICCommonState *s);
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void (*pre_save)(APICCommonState *s);
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void (*post_load)(APICCommonState *s);
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void (*reset)(APICCommonState *s);
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} APICCommonClass;
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struct APICCommonState {
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ICCDevice busdev;
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MemoryRegion io_memory;
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X86CPU *cpu;
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uint32_t apicbase;
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uint8_t id;
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uint8_t version;
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uint8_t arb_id;
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uint8_t tpr;
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uint32_t spurious_vec;
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uint8_t log_dest;
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uint8_t dest_mode;
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uint32_t isr[8]; /* in service register */
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uint32_t tmr[8]; /* trigger mode register */
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uint32_t irr[8]; /* interrupt request register */
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uint32_t lvt[APIC_LVT_NB];
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uint32_t esr; /* error register */
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uint32_t icr[2];
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uint32_t divide_conf;
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int count_shift;
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uint32_t initial_count;
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int64_t initial_count_load_time;
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int64_t next_time;
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int idx;
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QEMUTimer *timer;
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int64_t timer_expiry;
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int sipi_vector;
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int wait_for_sipi;
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uint32_t vapic_control;
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DeviceState *vapic;
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hwaddr vapic_paddr; /* note: persistence via kvmvapic */
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};
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typedef struct VAPICState {
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uint8_t tpr;
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uint8_t isr;
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uint8_t zero;
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uint8_t irr;
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uint8_t enabled;
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} QEMU_PACKED VAPICState;
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extern bool apic_report_tpr_access;
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bool apic_next_timer(APICCommonState *s, int64_t current_time);
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void apic_enable_vapic(struct uc_struct *uc, DeviceState *d, hwaddr paddr);
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void vapic_report_tpr_access(DeviceState *dev, CPUState *cpu, target_ulong ip,
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TPRAccess access);
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#endif /* !QEMU_APIC_INTERNAL_H */
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52
qemu/include/hw/i386/pc.h
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52
qemu/include/hw/i386/pc.h
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@@ -0,0 +1,52 @@
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#ifndef HW_PC_H
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#define HW_PC_H
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#include "hw/boards.h"
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/**
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* PCMachineState:
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*/
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struct PCMachineState {
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/*< private >*/
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MachineState parent_obj;
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uint64_t max_ram_below_4g;
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};
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#define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
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/**
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* PCMachineClass:
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*/
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struct PCMachineClass {
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/*< private >*/
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MachineClass parent_class;
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};
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typedef struct PCMachineState PCMachineState;
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typedef struct PCMachineClass PCMachineClass;
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#define TYPE_PC_MACHINE "generic-pc-machine"
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#define PC_MACHINE(uc, obj) \
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OBJECT_CHECK(uc, PCMachineState, (obj), TYPE_PC_MACHINE)
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#define PC_MACHINE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE)
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#define PC_MACHINE_CLASS(klass) \
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OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE)
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void pc_cpus_init(struct uc_struct *uc, const char *cpu_model);
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FWCfgState *pc_memory_init(MachineState *machine,
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MemoryRegion *system_memory,
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ram_addr_t begin,
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MemoryRegion **ram_memory);
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typedef void (*cpu_set_smm_t)(int smm, void *arg);
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void cpu_smm_register(cpu_set_smm_t callback, void *arg);
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void pc_machine_register_types(struct uc_struct *uc);
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void x86_cpu_register_types(struct uc_struct *uc);
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#define PC_DEFAULT_MACHINE_OPTIONS \
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.max_cpus = 255
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#endif
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