import
This commit is contained in:
Nguyen Anh Quynh
258
qemu/hw/intc/apic_common.c
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258
qemu/hw/intc/apic_common.c
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/*
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* APIC support - common bits of emulated and KVM kernel model
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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* Copyright (c) 2011 Jan Kiszka, Siemens AG
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "hw/i386/apic.h"
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#include "hw/i386/apic_internal.h"
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#include "hw/qdev.h"
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#include "uc_priv.h"
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void cpu_set_apic_base(struct uc_struct *uc, DeviceState *dev, uint64_t val)
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{
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if (dev) {
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APICCommonState *s = APIC_COMMON(uc, dev);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(uc, s);
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info->set_base(s, val);
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}
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}
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uint64_t cpu_get_apic_base(struct uc_struct *uc, DeviceState *dev)
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{
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if (dev) {
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APICCommonState *s = APIC_COMMON(uc, dev);
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return s->apicbase;
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} else {
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return MSR_IA32_APICBASE_BSP;
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}
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}
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void cpu_set_apic_tpr(struct uc_struct *uc, DeviceState *dev, uint8_t val)
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{
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APICCommonState *s;
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APICCommonClass *info;
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if (!dev) {
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return;
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}
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s = APIC_COMMON(uc, dev);
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info = APIC_COMMON_GET_CLASS(uc, s);
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info->set_tpr(s, val);
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}
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uint8_t cpu_get_apic_tpr(struct uc_struct *uc, DeviceState *dev)
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{
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APICCommonState *s;
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APICCommonClass *info;
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if (!dev) {
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return 0;
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}
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s = APIC_COMMON(uc, dev);
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info = APIC_COMMON_GET_CLASS(uc, s);
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return info->get_tpr(s);
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}
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void apic_enable_vapic(struct uc_struct *uc, DeviceState *dev, hwaddr paddr)
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{
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APICCommonState *s = APIC_COMMON(uc, dev);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(uc, s);
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s->vapic_paddr = paddr;
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info->vapic_base_update(s);
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}
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void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
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TPRAccess access)
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{
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//APICCommonState *s = APIC_COMMON(NULL, dev);
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//vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
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}
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bool apic_next_timer(APICCommonState *s, int64_t current_time)
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{
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int64_t d;
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/* We need to store the timer state separately to support APIC
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* implementations that maintain a non-QEMU timer, e.g. inside the
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* host kernel. This open-coded state allows us to migrate between
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* both models. */
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s->timer_expiry = -1;
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if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
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return false;
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}
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d = (current_time - s->initial_count_load_time) >> s->count_shift;
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if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
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if (!s->initial_count) {
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return false;
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}
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d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
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((uint64_t)s->initial_count + 1);
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} else {
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if (d >= s->initial_count) {
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return false;
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}
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d = (uint64_t)s->initial_count + 1;
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}
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s->next_time = s->initial_count_load_time + (d << s->count_shift);
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s->timer_expiry = s->next_time;
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return true;
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}
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void apic_init_reset(struct uc_struct *uc, DeviceState *dev)
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{
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APICCommonState *s = APIC_COMMON(uc, dev);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(uc, s);
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int i;
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if (!s) {
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return;
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}
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s->tpr = 0;
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s->spurious_vec = 0xff;
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s->log_dest = 0;
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s->dest_mode = 0xf;
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memset(s->isr, 0, sizeof(s->isr));
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memset(s->tmr, 0, sizeof(s->tmr));
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memset(s->irr, 0, sizeof(s->irr));
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for (i = 0; i < APIC_LVT_NB; i++) {
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s->lvt[i] = APIC_LVT_MASKED;
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}
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s->esr = 0;
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memset(s->icr, 0, sizeof(s->icr));
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s->divide_conf = 0;
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s->count_shift = 0;
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s->initial_count = 0;
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s->initial_count_load_time = 0;
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s->next_time = 0;
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s->wait_for_sipi = !cpu_is_bsp(s->cpu);
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if (s->timer) {
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timer_del(s->timer);
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}
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s->timer_expiry = -1;
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if (info->reset) {
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info->reset(s);
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}
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}
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void apic_designate_bsp(struct uc_struct *uc, DeviceState *dev)
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{
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if (dev == NULL) {
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return;
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}
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APICCommonState *s = APIC_COMMON(uc, dev);
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s->apicbase |= MSR_IA32_APICBASE_BSP;
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}
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static void apic_reset_common(struct uc_struct *uc, DeviceState *dev)
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{
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APICCommonState *s = APIC_COMMON(uc, dev);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(uc, s);
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bool bsp;
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bsp = cpu_is_bsp(s->cpu);
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s->apicbase = APIC_DEFAULT_ADDRESS |
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(bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
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s->vapic_paddr = 0;
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info->vapic_base_update(s);
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apic_init_reset(uc, dev);
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if (bsp) {
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/*
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* LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
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* time typically by BIOS, so PIC interrupt can be delivered to the
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* processor when local APIC is enabled.
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*/
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s->lvt[APIC_LVT_LINT0] = 0x700;
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}
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}
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static void apic_common_realize(struct uc_struct *uc, DeviceState *dev, Error **errp)
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{
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APICCommonState *s = APIC_COMMON(uc, dev);
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APICCommonClass *info;
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if (uc->apic_no >= MAX_APICS) {
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error_setg(errp, "%s initialization failed.",
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object_get_typename(OBJECT(dev)));
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return;
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}
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s->idx = uc->apic_no++;
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info = APIC_COMMON_GET_CLASS(uc, s);
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info->realize(uc, dev, errp);
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if (!uc->mmio_registered) {
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ICCBus *b = ICC_BUS(uc, qdev_get_parent_bus(dev));
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memory_region_add_subregion(b->apic_address_space, 0, &s->io_memory);
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uc->mmio_registered = true;
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}
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/* Note: We need at least 1M to map the VAPIC option ROM */
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if (!uc->vapic && s->vapic_control & VAPIC_ENABLE_MASK) {
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// ram_size >= 1024 * 1024) { // FIXME
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uc->vapic = NULL;
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}
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s->vapic = uc->vapic;
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if (uc->apic_report_tpr_access && info->enable_tpr_reporting) {
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info->enable_tpr_reporting(s, true);
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}
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}
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static void apic_common_class_init(struct uc_struct *uc, ObjectClass *klass, void *data)
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{
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ICCDeviceClass *idc = ICC_DEVICE_CLASS(uc, klass);
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DeviceClass *dc = DEVICE_CLASS(uc, klass);
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dc->reset = apic_reset_common;
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idc->realize = apic_common_realize;
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/*
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* Reason: APIC and CPU need to be wired up by
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* x86_cpu_apic_create()
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*/
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dc->cannot_instantiate_with_device_add_yet = true;
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//printf("... init apic common class\n");
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}
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static const TypeInfo apic_common_type = {
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.name = TYPE_APIC_COMMON,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(APICCommonState),
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.class_size = sizeof(APICCommonClass),
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.class_init = apic_common_class_init,
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.abstract = true,
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};
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void apic_common_register_types(struct uc_struct *uc)
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{
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//printf("... register apic common\n");
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type_register_static(uc, &apic_common_type);
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}
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