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Simplify reg_read/reg_write, obtaining a perf boost.

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Single reg_read/reg_write is now about 25% faster.
This commit is contained in:
Robert Xiao
2023-05-11 22:54:03 -07:00
parent 074566cf69
commit 30d202b89e
40 changed files with 563 additions and 1403 deletions
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117
qemu/target/riscv/unicorn.c
View File

@@ -77,11 +77,13 @@ static void riscv_release(void *ctx)
}
}
void riscv_reg_reset(struct uc_struct *uc) {}
static void reg_reset(struct uc_struct *uc) {}
static uc_err reg_read(CPURISCVState *env, unsigned int regid, void *value,
size_t *size)
DEFAULT_VISIBILITY
uc_err reg_read(void *_env, int mode, unsigned int regid, void *value,
size_t *size)
{
CPURISCVState *env = _env;
uc_err ret = UC_ERR_ARG;
if (regid >= UC_RISCV_REG_X0 && regid <= UC_RISCV_REG_X31) {
@@ -127,9 +129,11 @@ static uc_err reg_read(CPURISCVState *env, unsigned int regid, void *value,
return ret;
}
static uc_err reg_write(CPURISCVState *env, unsigned int regid,
const void *value, size_t *size, int *setpc)
DEFAULT_VISIBILITY
uc_err reg_write(void *_env, int mode, unsigned int regid, const void *value,
size_t *size, int *setpc)
{
CPURISCVState *env = _env;
uc_err ret = UC_ERR_ARG;
if (regid >= UC_RISCV_REG_X0 && regid <= UC_RISCV_REG_X31) {
@@ -175,96 +179,6 @@ static uc_err reg_write(CPURISCVState *env, unsigned int regid,
return ret;
}
static uc_err reg_read_batch(CPURISCVState *env, unsigned int *regs,
void *const *vals, size_t *sizes, int count)
{
int i;
for (i = 0; i < count; i++) {
unsigned int regid = regs[i];
void *value = vals[i];
uc_err err = reg_read(env, regid, value, sizes ? sizes + i : NULL);
if (err) {
return err;
}
}
return UC_ERR_OK;
}
static uc_err reg_write_batch(CPURISCVState *env, unsigned int *regs,
const void *const *vals, size_t *sizes, int count,
int *setpc)
{
int i;
for (i = 0; i < count; i++) {
unsigned int regid = regs[i];
const void *value = vals[i];
uc_err err =
reg_write(env, regid, value, sizes ? sizes + i : NULL, setpc);
if (err) {
return err;
}
}
return UC_ERR_OK;
}
int riscv_reg_read(struct uc_struct *uc, unsigned int *regs, void *const *vals,
size_t *sizes, int count)
{
CPURISCVState *env = &(RISCV_CPU(uc->cpu)->env);
return reg_read_batch(env, regs, vals, sizes, count);
}
int riscv_reg_write(struct uc_struct *uc, unsigned int *regs,
const void *const *vals, size_t *sizes, int count)
{
CPURISCVState *env = &(RISCV_CPU(uc->cpu)->env);
int setpc = 0;
uc_err err = reg_write_batch(env, regs, vals, sizes, count, &setpc);
if (err) {
return err;
}
if (setpc) {
// force to quit execution and flush TB
uc->quit_request = true;
break_translation_loop(uc);
}
return UC_ERR_OK;
}
DEFAULT_VISIBILITY
#ifdef TARGET_RISCV32
int riscv32_context_reg_read(struct uc_context *ctx, unsigned int *regs,
void *const *vals, size_t *sizes, int count)
#else
/* TARGET_RISCV64 */
int riscv64_context_reg_read(struct uc_context *ctx, unsigned int *regs,
void *const *vals, size_t *sizes, int count)
#endif
{
CPURISCVState *env = (CPURISCVState *)ctx->data;
return reg_read_batch(env, regs, vals, sizes, count);
}
DEFAULT_VISIBILITY
#ifdef TARGET_RISCV32
int riscv32_context_reg_write(struct uc_context *ctx, unsigned int *regs,
const void *const *vals, size_t *sizes, int count)
#else
/* TARGET_RISCV64 */
int riscv64_context_reg_write(struct uc_context *ctx, unsigned int *regs,
const void *const *vals, size_t *sizes, int count)
#endif
{
CPURISCVState *env = (CPURISCVState *)ctx->data;
int setpc = 0;
return reg_write_batch(env, regs, vals, sizes, count, &setpc);
}
static bool riscv_stop_interrupt(struct uc_struct *uc, int intno)
{
// detect stop exception
@@ -298,16 +212,11 @@ static int riscv_cpus_init(struct uc_struct *uc, const char *cpu_model)
}
DEFAULT_VISIBILITY
#ifdef TARGET_RISCV32
void riscv32_uc_init(struct uc_struct *uc)
#else
/* TARGET_RISCV64 */
void riscv64_uc_init(struct uc_struct *uc)
#endif
void uc_init(struct uc_struct *uc)
{
uc->reg_read = riscv_reg_read;
uc->reg_write = riscv_reg_write;
uc->reg_reset = riscv_reg_reset;
uc->reg_read = reg_read;
uc->reg_write = reg_write;
uc->reg_reset = reg_reset;
uc->release = riscv_release;
uc->set_pc = riscv_set_pc;
uc->get_pc = riscv_get_pc;

29
qemu/target/riscv/unicorn.h
View File

@@ -6,24 +6,15 @@
#define UC_QEMU_TARGET_RISCV_H
// functions to read & write registers
int riscv_reg_read(struct uc_struct *uc, unsigned int *regs, void *const *vals,
size_t *sizes, int count);
int riscv_reg_write(struct uc_struct *uc, unsigned int *regs,
const void *const *vals, size_t *sizes, int count);
uc_err reg_read_riscv32(void *env, int mode, unsigned int regid, void *value,
size_t *size);
uc_err reg_read_riscv64(void *env, int mode, unsigned int regid, void *value,
size_t *size);
uc_err reg_write_riscv32(void *env, int mode, unsigned int regid,
const void *value, size_t *size, int *setpc);
uc_err reg_write_riscv64(void *env, int mode, unsigned int regid,
const void *value, size_t *size, int *setpc);
int riscv32_context_reg_read(struct uc_context *ctx, unsigned int *regs,
void *const *vals, size_t *sizes, int count);
int riscv32_context_reg_write(struct uc_context *ctx, unsigned int *regs,
const void *const *vals, size_t *sizes,
int count);
int riscv64_context_reg_read(struct uc_context *ctx, unsigned int *regs,
void *const *vals, size_t *sizes, int count);
int riscv64_context_reg_write(struct uc_context *ctx, unsigned int *regs,
const void *const *vals, size_t *sizes,
int count);
void riscv_reg_reset(struct uc_struct *uc);
void riscv32_uc_init(struct uc_struct *uc);
void riscv64_uc_init(struct uc_struct *uc);
void uc_init_riscv32(struct uc_struct *uc);
void uc_init_riscv64(struct uc_struct *uc);
#endif