add cpu model to architectures for rust bindings

bindings/rust/src/arm.rs

@@ -171,3 +171,53 @@ impl From<RegisterARM> for i32 {
         r as i32
     }
 }
+
+#[repr(i32)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
+pub enum ArmCpuModel {
+    UC_CPU_ARM_926 = 0,
+    UC_CPU_ARM_946 = 1,
+    UC_CPU_ARM_1026 = 2,
+    UC_CPU_ARM_1136_R2 = 3,
+    UC_CPU_ARM_1136 = 4,
+    UC_CPU_ARM_1176 = 5,
+    UC_CPU_ARM_11MPCORE = 6,
+    UC_CPU_ARM_CORTEX_M0 = 7,
+    UC_CPU_ARM_CORTEX_M3 = 8,
+    UC_CPU_ARM_CORTEX_M4 = 9,
+    UC_CPU_ARM_CORTEX_M7 = 10,
+    UC_CPU_ARM_CORTEX_M33 = 11,
+    UC_CPU_ARM_CORTEX_R5 = 12,
+    UC_CPU_ARM_CORTEX_R5F = 13,
+    UC_CPU_ARM_CORTEX_A7 = 14,
+    UC_CPU_ARM_CORTEX_A8 = 15,
+    UC_CPU_ARM_CORTEX_A9 = 16,
+    UC_CPU_ARM_CORTEX_A15 = 17,
+    UC_CPU_ARM_TI925T = 18,
+    UC_CPU_ARM_SA1100 = 19,
+    UC_CPU_ARM_SA1110 = 20,
+    UC_CPU_ARM_PXA250 = 21,
+    UC_CPU_ARM_PXA255 = 22,
+    UC_CPU_ARM_PXA260 = 23,
+    UC_CPU_ARM_PXA261 = 24,
+    UC_CPU_ARM_PXA262 = 25,
+    UC_CPU_ARM_PXA270 = 26,
+    UC_CPU_ARM_PXA270A0 = 27,
+    UC_CPU_ARM_PXA270A1 = 28,
+    UC_CPU_ARM_PXA270B0 = 29,
+    UC_CPU_ARM_PXA270B1 = 30,
+    UC_CPU_ARM_PXA270C0 = 31,
+    UC_CPU_ARM_PXA270C5 = 32,
+}
+
+impl From<ArmCpuModel> for i32 {
+    fn from(value: ArmCpuModel) -> Self {
+        value as i32
+    }
+}
+
+impl From<&ArmCpuModel> for i32 {
+    fn from(value: &ArmCpuModel) -> Self {
+        *value as i32
+    }
+}