mips: advance PC for SYSCALL instruction. this fixes issue #157

qemu/cpu-exec.c

@@ -136,6 +136,9 @@ int cpu_exec(struct uc_struct *uc, CPUArchState *env)   // qq
                     // point EIP to the next instruction after INT
                     env->eip = env->exception_next_eip;
 #endif
+#if defined(TARGET_MIPS) || defined(TARGET_MIPS64)
+                    env->active_tc.PC = uc->next_pc;
+#endif
 #endif
                 }
             }

qemu/target-mips/translate.c

@@ -19348,6 +19348,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
         switch (ctx.bstate) {
         case BS_STOP:
             gen_goto_tb(&ctx, 0, ctx.pc);
+            env->uc->next_pc = ctx.pc;
             break;
         case BS_NONE:
             save_cpu_state(&ctx, 0);

qemu/tcg/tcg.c

@@ -2586,8 +2586,13 @@ int tcg_gen_code(TCGContext *s, tcg_insn_unit *gen_code_buf)    // qq
     }
 #endif
 
+    //printf("====== before gen code\n");
+    //tcg_dump_ops(s);
     tcg_gen_code_common(s, gen_code_buf, -1);   // qq
 
+    //printf("====== after gen code\n");
+    //tcg_dump_ops(s);
+
     /* flush instruction cache */
     flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);