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bindings: Rename dotnet project to UnicornEngine

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Add a few more properties to prepare a nuget package
This commit is contained in:
TSR Berry
2022-10-31 22:56:44 +01:00
parent a16f4ff911
commit 1d12e8778b
25 changed files with 39 additions and 33 deletions
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200
bindings/dotnet/UnicornEngine/Const/Arm.fs Normal file
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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
namespace UnicornEngine.Const
open System
[<AutoOpen>]
module Arm =
// ARM CPU
let UC_CPU_ARM_926 = 0
let UC_CPU_ARM_946 = 1
let UC_CPU_ARM_1026 = 2
let UC_CPU_ARM_1136_R2 = 3
let UC_CPU_ARM_1136 = 4
let UC_CPU_ARM_1176 = 5
let UC_CPU_ARM_11MPCORE = 6
let UC_CPU_ARM_CORTEX_M0 = 7
let UC_CPU_ARM_CORTEX_M3 = 8
let UC_CPU_ARM_CORTEX_M4 = 9
let UC_CPU_ARM_CORTEX_M7 = 10
let UC_CPU_ARM_CORTEX_M33 = 11
let UC_CPU_ARM_CORTEX_R5 = 12
let UC_CPU_ARM_CORTEX_R5F = 13
let UC_CPU_ARM_CORTEX_A7 = 14
let UC_CPU_ARM_CORTEX_A8 = 15
let UC_CPU_ARM_CORTEX_A9 = 16
let UC_CPU_ARM_CORTEX_A15 = 17
let UC_CPU_ARM_TI925T = 18
let UC_CPU_ARM_SA1100 = 19
let UC_CPU_ARM_SA1110 = 20
let UC_CPU_ARM_PXA250 = 21
let UC_CPU_ARM_PXA255 = 22
let UC_CPU_ARM_PXA260 = 23
let UC_CPU_ARM_PXA261 = 24
let UC_CPU_ARM_PXA262 = 25
let UC_CPU_ARM_PXA270 = 26
let UC_CPU_ARM_PXA270A0 = 27
let UC_CPU_ARM_PXA270A1 = 28
let UC_CPU_ARM_PXA270B0 = 29
let UC_CPU_ARM_PXA270B1 = 30
let UC_CPU_ARM_PXA270C0 = 31
let UC_CPU_ARM_PXA270C5 = 32
let UC_CPU_ARM_MAX = 33
let UC_CPU_ARM_ENDING = 34
// ARM registers
let UC_ARM_REG_INVALID = 0
let UC_ARM_REG_APSR = 1
let UC_ARM_REG_APSR_NZCV = 2
let UC_ARM_REG_CPSR = 3
let UC_ARM_REG_FPEXC = 4
let UC_ARM_REG_FPINST = 5
let UC_ARM_REG_FPSCR = 6
let UC_ARM_REG_FPSCR_NZCV = 7
let UC_ARM_REG_FPSID = 8
let UC_ARM_REG_ITSTATE = 9
let UC_ARM_REG_LR = 10
let UC_ARM_REG_PC = 11
let UC_ARM_REG_SP = 12
let UC_ARM_REG_SPSR = 13
let UC_ARM_REG_D0 = 14
let UC_ARM_REG_D1 = 15
let UC_ARM_REG_D2 = 16
let UC_ARM_REG_D3 = 17
let UC_ARM_REG_D4 = 18
let UC_ARM_REG_D5 = 19
let UC_ARM_REG_D6 = 20
let UC_ARM_REG_D7 = 21
let UC_ARM_REG_D8 = 22
let UC_ARM_REG_D9 = 23
let UC_ARM_REG_D10 = 24
let UC_ARM_REG_D11 = 25
let UC_ARM_REG_D12 = 26
let UC_ARM_REG_D13 = 27
let UC_ARM_REG_D14 = 28
let UC_ARM_REG_D15 = 29
let UC_ARM_REG_D16 = 30
let UC_ARM_REG_D17 = 31
let UC_ARM_REG_D18 = 32
let UC_ARM_REG_D19 = 33
let UC_ARM_REG_D20 = 34
let UC_ARM_REG_D21 = 35
let UC_ARM_REG_D22 = 36
let UC_ARM_REG_D23 = 37
let UC_ARM_REG_D24 = 38
let UC_ARM_REG_D25 = 39
let UC_ARM_REG_D26 = 40
let UC_ARM_REG_D27 = 41
let UC_ARM_REG_D28 = 42
let UC_ARM_REG_D29 = 43
let UC_ARM_REG_D30 = 44
let UC_ARM_REG_D31 = 45
let UC_ARM_REG_FPINST2 = 46
let UC_ARM_REG_MVFR0 = 47
let UC_ARM_REG_MVFR1 = 48
let UC_ARM_REG_MVFR2 = 49
let UC_ARM_REG_Q0 = 50
let UC_ARM_REG_Q1 = 51
let UC_ARM_REG_Q2 = 52
let UC_ARM_REG_Q3 = 53
let UC_ARM_REG_Q4 = 54
let UC_ARM_REG_Q5 = 55
let UC_ARM_REG_Q6 = 56
let UC_ARM_REG_Q7 = 57
let UC_ARM_REG_Q8 = 58
let UC_ARM_REG_Q9 = 59
let UC_ARM_REG_Q10 = 60
let UC_ARM_REG_Q11 = 61
let UC_ARM_REG_Q12 = 62
let UC_ARM_REG_Q13 = 63
let UC_ARM_REG_Q14 = 64
let UC_ARM_REG_Q15 = 65
let UC_ARM_REG_R0 = 66
let UC_ARM_REG_R1 = 67
let UC_ARM_REG_R2 = 68
let UC_ARM_REG_R3 = 69
let UC_ARM_REG_R4 = 70
let UC_ARM_REG_R5 = 71
let UC_ARM_REG_R6 = 72
let UC_ARM_REG_R7 = 73
let UC_ARM_REG_R8 = 74
let UC_ARM_REG_R9 = 75
let UC_ARM_REG_R10 = 76
let UC_ARM_REG_R11 = 77
let UC_ARM_REG_R12 = 78
let UC_ARM_REG_S0 = 79
let UC_ARM_REG_S1 = 80
let UC_ARM_REG_S2 = 81
let UC_ARM_REG_S3 = 82
let UC_ARM_REG_S4 = 83
let UC_ARM_REG_S5 = 84
let UC_ARM_REG_S6 = 85
let UC_ARM_REG_S7 = 86
let UC_ARM_REG_S8 = 87
let UC_ARM_REG_S9 = 88
let UC_ARM_REG_S10 = 89
let UC_ARM_REG_S11 = 90
let UC_ARM_REG_S12 = 91
let UC_ARM_REG_S13 = 92
let UC_ARM_REG_S14 = 93
let UC_ARM_REG_S15 = 94
let UC_ARM_REG_S16 = 95
let UC_ARM_REG_S17 = 96
let UC_ARM_REG_S18 = 97
let UC_ARM_REG_S19 = 98
let UC_ARM_REG_S20 = 99
let UC_ARM_REG_S21 = 100
let UC_ARM_REG_S22 = 101
let UC_ARM_REG_S23 = 102
let UC_ARM_REG_S24 = 103
let UC_ARM_REG_S25 = 104
let UC_ARM_REG_S26 = 105
let UC_ARM_REG_S27 = 106
let UC_ARM_REG_S28 = 107
let UC_ARM_REG_S29 = 108
let UC_ARM_REG_S30 = 109
let UC_ARM_REG_S31 = 110
let UC_ARM_REG_C1_C0_2 = 111
let UC_ARM_REG_C13_C0_2 = 112
let UC_ARM_REG_C13_C0_3 = 113
let UC_ARM_REG_IPSR = 114
let UC_ARM_REG_MSP = 115
let UC_ARM_REG_PSP = 116
let UC_ARM_REG_CONTROL = 117
let UC_ARM_REG_IAPSR = 118
let UC_ARM_REG_EAPSR = 119
let UC_ARM_REG_XPSR = 120
let UC_ARM_REG_EPSR = 121
let UC_ARM_REG_IEPSR = 122
let UC_ARM_REG_PRIMASK = 123
let UC_ARM_REG_BASEPRI = 124
let UC_ARM_REG_BASEPRI_MAX = 125
let UC_ARM_REG_FAULTMASK = 126
let UC_ARM_REG_APSR_NZCVQ = 127
let UC_ARM_REG_APSR_G = 128
let UC_ARM_REG_APSR_NZCVQG = 129
let UC_ARM_REG_IAPSR_NZCVQ = 130
let UC_ARM_REG_IAPSR_G = 131
let UC_ARM_REG_IAPSR_NZCVQG = 132
let UC_ARM_REG_EAPSR_NZCVQ = 133
let UC_ARM_REG_EAPSR_G = 134
let UC_ARM_REG_EAPSR_NZCVQG = 135
let UC_ARM_REG_XPSR_NZCVQ = 136
let UC_ARM_REG_XPSR_G = 137
let UC_ARM_REG_XPSR_NZCVQG = 138
let UC_ARM_REG_CP_REG = 139
let UC_ARM_REG_ENDING = 140
// alias registers
let UC_ARM_REG_R13 = 12
let UC_ARM_REG_R14 = 10
let UC_ARM_REG_R15 = 11
let UC_ARM_REG_SB = 75
let UC_ARM_REG_SL = 76
let UC_ARM_REG_FP = 77
let UC_ARM_REG_IP = 78

341
bindings/dotnet/UnicornEngine/Const/Arm64.fs Normal file
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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
namespace UnicornEngine.Const
open System
[<AutoOpen>]
module Arm64 =
// ARM64 CPU
let UC_CPU_ARM64_A57 = 0
let UC_CPU_ARM64_A53 = 1
let UC_CPU_ARM64_A72 = 2
let UC_CPU_ARM64_MAX = 3
let UC_CPU_ARM64_ENDING = 4
// ARM64 registers
let UC_ARM64_REG_INVALID = 0
let UC_ARM64_REG_X29 = 1
let UC_ARM64_REG_X30 = 2
let UC_ARM64_REG_NZCV = 3
let UC_ARM64_REG_SP = 4
let UC_ARM64_REG_WSP = 5
let UC_ARM64_REG_WZR = 6
let UC_ARM64_REG_XZR = 7
let UC_ARM64_REG_B0 = 8
let UC_ARM64_REG_B1 = 9
let UC_ARM64_REG_B2 = 10
let UC_ARM64_REG_B3 = 11
let UC_ARM64_REG_B4 = 12
let UC_ARM64_REG_B5 = 13
let UC_ARM64_REG_B6 = 14
let UC_ARM64_REG_B7 = 15
let UC_ARM64_REG_B8 = 16
let UC_ARM64_REG_B9 = 17
let UC_ARM64_REG_B10 = 18
let UC_ARM64_REG_B11 = 19
let UC_ARM64_REG_B12 = 20
let UC_ARM64_REG_B13 = 21
let UC_ARM64_REG_B14 = 22
let UC_ARM64_REG_B15 = 23
let UC_ARM64_REG_B16 = 24
let UC_ARM64_REG_B17 = 25
let UC_ARM64_REG_B18 = 26
let UC_ARM64_REG_B19 = 27
let UC_ARM64_REG_B20 = 28
let UC_ARM64_REG_B21 = 29
let UC_ARM64_REG_B22 = 30
let UC_ARM64_REG_B23 = 31
let UC_ARM64_REG_B24 = 32
let UC_ARM64_REG_B25 = 33
let UC_ARM64_REG_B26 = 34
let UC_ARM64_REG_B27 = 35
let UC_ARM64_REG_B28 = 36
let UC_ARM64_REG_B29 = 37
let UC_ARM64_REG_B30 = 38
let UC_ARM64_REG_B31 = 39
let UC_ARM64_REG_D0 = 40
let UC_ARM64_REG_D1 = 41
let UC_ARM64_REG_D2 = 42
let UC_ARM64_REG_D3 = 43
let UC_ARM64_REG_D4 = 44
let UC_ARM64_REG_D5 = 45
let UC_ARM64_REG_D6 = 46
let UC_ARM64_REG_D7 = 47
let UC_ARM64_REG_D8 = 48
let UC_ARM64_REG_D9 = 49
let UC_ARM64_REG_D10 = 50
let UC_ARM64_REG_D11 = 51
let UC_ARM64_REG_D12 = 52
let UC_ARM64_REG_D13 = 53
let UC_ARM64_REG_D14 = 54
let UC_ARM64_REG_D15 = 55
let UC_ARM64_REG_D16 = 56
let UC_ARM64_REG_D17 = 57
let UC_ARM64_REG_D18 = 58
let UC_ARM64_REG_D19 = 59
let UC_ARM64_REG_D20 = 60
let UC_ARM64_REG_D21 = 61
let UC_ARM64_REG_D22 = 62
let UC_ARM64_REG_D23 = 63
let UC_ARM64_REG_D24 = 64
let UC_ARM64_REG_D25 = 65
let UC_ARM64_REG_D26 = 66
let UC_ARM64_REG_D27 = 67
let UC_ARM64_REG_D28 = 68
let UC_ARM64_REG_D29 = 69
let UC_ARM64_REG_D30 = 70
let UC_ARM64_REG_D31 = 71
let UC_ARM64_REG_H0 = 72
let UC_ARM64_REG_H1 = 73
let UC_ARM64_REG_H2 = 74
let UC_ARM64_REG_H3 = 75
let UC_ARM64_REG_H4 = 76
let UC_ARM64_REG_H5 = 77
let UC_ARM64_REG_H6 = 78
let UC_ARM64_REG_H7 = 79
let UC_ARM64_REG_H8 = 80
let UC_ARM64_REG_H9 = 81
let UC_ARM64_REG_H10 = 82
let UC_ARM64_REG_H11 = 83
let UC_ARM64_REG_H12 = 84
let UC_ARM64_REG_H13 = 85
let UC_ARM64_REG_H14 = 86
let UC_ARM64_REG_H15 = 87
let UC_ARM64_REG_H16 = 88
let UC_ARM64_REG_H17 = 89
let UC_ARM64_REG_H18 = 90
let UC_ARM64_REG_H19 = 91
let UC_ARM64_REG_H20 = 92
let UC_ARM64_REG_H21 = 93
let UC_ARM64_REG_H22 = 94
let UC_ARM64_REG_H23 = 95
let UC_ARM64_REG_H24 = 96
let UC_ARM64_REG_H25 = 97
let UC_ARM64_REG_H26 = 98
let UC_ARM64_REG_H27 = 99
let UC_ARM64_REG_H28 = 100
let UC_ARM64_REG_H29 = 101
let UC_ARM64_REG_H30 = 102
let UC_ARM64_REG_H31 = 103
let UC_ARM64_REG_Q0 = 104
let UC_ARM64_REG_Q1 = 105
let UC_ARM64_REG_Q2 = 106
let UC_ARM64_REG_Q3 = 107
let UC_ARM64_REG_Q4 = 108
let UC_ARM64_REG_Q5 = 109
let UC_ARM64_REG_Q6 = 110
let UC_ARM64_REG_Q7 = 111
let UC_ARM64_REG_Q8 = 112
let UC_ARM64_REG_Q9 = 113
let UC_ARM64_REG_Q10 = 114
let UC_ARM64_REG_Q11 = 115
let UC_ARM64_REG_Q12 = 116
let UC_ARM64_REG_Q13 = 117
let UC_ARM64_REG_Q14 = 118
let UC_ARM64_REG_Q15 = 119
let UC_ARM64_REG_Q16 = 120
let UC_ARM64_REG_Q17 = 121
let UC_ARM64_REG_Q18 = 122
let UC_ARM64_REG_Q19 = 123
let UC_ARM64_REG_Q20 = 124
let UC_ARM64_REG_Q21 = 125
let UC_ARM64_REG_Q22 = 126
let UC_ARM64_REG_Q23 = 127
let UC_ARM64_REG_Q24 = 128
let UC_ARM64_REG_Q25 = 129
let UC_ARM64_REG_Q26 = 130
let UC_ARM64_REG_Q27 = 131
let UC_ARM64_REG_Q28 = 132
let UC_ARM64_REG_Q29 = 133
let UC_ARM64_REG_Q30 = 134
let UC_ARM64_REG_Q31 = 135
let UC_ARM64_REG_S0 = 136
let UC_ARM64_REG_S1 = 137
let UC_ARM64_REG_S2 = 138
let UC_ARM64_REG_S3 = 139
let UC_ARM64_REG_S4 = 140
let UC_ARM64_REG_S5 = 141
let UC_ARM64_REG_S6 = 142
let UC_ARM64_REG_S7 = 143
let UC_ARM64_REG_S8 = 144
let UC_ARM64_REG_S9 = 145
let UC_ARM64_REG_S10 = 146
let UC_ARM64_REG_S11 = 147
let UC_ARM64_REG_S12 = 148
let UC_ARM64_REG_S13 = 149
let UC_ARM64_REG_S14 = 150
let UC_ARM64_REG_S15 = 151
let UC_ARM64_REG_S16 = 152
let UC_ARM64_REG_S17 = 153
let UC_ARM64_REG_S18 = 154
let UC_ARM64_REG_S19 = 155
let UC_ARM64_REG_S20 = 156
let UC_ARM64_REG_S21 = 157
let UC_ARM64_REG_S22 = 158
let UC_ARM64_REG_S23 = 159
let UC_ARM64_REG_S24 = 160
let UC_ARM64_REG_S25 = 161
let UC_ARM64_REG_S26 = 162
let UC_ARM64_REG_S27 = 163
let UC_ARM64_REG_S28 = 164
let UC_ARM64_REG_S29 = 165
let UC_ARM64_REG_S30 = 166
let UC_ARM64_REG_S31 = 167
let UC_ARM64_REG_W0 = 168
let UC_ARM64_REG_W1 = 169
let UC_ARM64_REG_W2 = 170
let UC_ARM64_REG_W3 = 171
let UC_ARM64_REG_W4 = 172
let UC_ARM64_REG_W5 = 173
let UC_ARM64_REG_W6 = 174
let UC_ARM64_REG_W7 = 175
let UC_ARM64_REG_W8 = 176
let UC_ARM64_REG_W9 = 177
let UC_ARM64_REG_W10 = 178
let UC_ARM64_REG_W11 = 179
let UC_ARM64_REG_W12 = 180
let UC_ARM64_REG_W13 = 181
let UC_ARM64_REG_W14 = 182
let UC_ARM64_REG_W15 = 183
let UC_ARM64_REG_W16 = 184
let UC_ARM64_REG_W17 = 185
let UC_ARM64_REG_W18 = 186
let UC_ARM64_REG_W19 = 187
let UC_ARM64_REG_W20 = 188
let UC_ARM64_REG_W21 = 189
let UC_ARM64_REG_W22 = 190
let UC_ARM64_REG_W23 = 191
let UC_ARM64_REG_W24 = 192
let UC_ARM64_REG_W25 = 193
let UC_ARM64_REG_W26 = 194
let UC_ARM64_REG_W27 = 195
let UC_ARM64_REG_W28 = 196
let UC_ARM64_REG_W29 = 197
let UC_ARM64_REG_W30 = 198
let UC_ARM64_REG_X0 = 199
let UC_ARM64_REG_X1 = 200
let UC_ARM64_REG_X2 = 201
let UC_ARM64_REG_X3 = 202
let UC_ARM64_REG_X4 = 203
let UC_ARM64_REG_X5 = 204
let UC_ARM64_REG_X6 = 205
let UC_ARM64_REG_X7 = 206
let UC_ARM64_REG_X8 = 207
let UC_ARM64_REG_X9 = 208
let UC_ARM64_REG_X10 = 209
let UC_ARM64_REG_X11 = 210
let UC_ARM64_REG_X12 = 211
let UC_ARM64_REG_X13 = 212
let UC_ARM64_REG_X14 = 213
let UC_ARM64_REG_X15 = 214
let UC_ARM64_REG_X16 = 215
let UC_ARM64_REG_X17 = 216
let UC_ARM64_REG_X18 = 217
let UC_ARM64_REG_X19 = 218
let UC_ARM64_REG_X20 = 219
let UC_ARM64_REG_X21 = 220
let UC_ARM64_REG_X22 = 221
let UC_ARM64_REG_X23 = 222
let UC_ARM64_REG_X24 = 223
let UC_ARM64_REG_X25 = 224
let UC_ARM64_REG_X26 = 225
let UC_ARM64_REG_X27 = 226
let UC_ARM64_REG_X28 = 227
let UC_ARM64_REG_V0 = 228
let UC_ARM64_REG_V1 = 229
let UC_ARM64_REG_V2 = 230
let UC_ARM64_REG_V3 = 231
let UC_ARM64_REG_V4 = 232
let UC_ARM64_REG_V5 = 233
let UC_ARM64_REG_V6 = 234
let UC_ARM64_REG_V7 = 235
let UC_ARM64_REG_V8 = 236
let UC_ARM64_REG_V9 = 237
let UC_ARM64_REG_V10 = 238
let UC_ARM64_REG_V11 = 239
let UC_ARM64_REG_V12 = 240
let UC_ARM64_REG_V13 = 241
let UC_ARM64_REG_V14 = 242
let UC_ARM64_REG_V15 = 243
let UC_ARM64_REG_V16 = 244
let UC_ARM64_REG_V17 = 245
let UC_ARM64_REG_V18 = 246
let UC_ARM64_REG_V19 = 247
let UC_ARM64_REG_V20 = 248
let UC_ARM64_REG_V21 = 249
let UC_ARM64_REG_V22 = 250
let UC_ARM64_REG_V23 = 251
let UC_ARM64_REG_V24 = 252
let UC_ARM64_REG_V25 = 253
let UC_ARM64_REG_V26 = 254
let UC_ARM64_REG_V27 = 255
let UC_ARM64_REG_V28 = 256
let UC_ARM64_REG_V29 = 257
let UC_ARM64_REG_V30 = 258
let UC_ARM64_REG_V31 = 259
// pseudo registers
let UC_ARM64_REG_PC = 260
let UC_ARM64_REG_CPACR_EL1 = 261
// thread registers, depreciated, use UC_ARM64_REG_CP_REG instead
let UC_ARM64_REG_TPIDR_EL0 = 262
let UC_ARM64_REG_TPIDRRO_EL0 = 263
let UC_ARM64_REG_TPIDR_EL1 = 264
let UC_ARM64_REG_PSTATE = 265
// exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead
let UC_ARM64_REG_ELR_EL0 = 266
let UC_ARM64_REG_ELR_EL1 = 267
let UC_ARM64_REG_ELR_EL2 = 268
let UC_ARM64_REG_ELR_EL3 = 269
// stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead
let UC_ARM64_REG_SP_EL0 = 270
let UC_ARM64_REG_SP_EL1 = 271
let UC_ARM64_REG_SP_EL2 = 272
let UC_ARM64_REG_SP_EL3 = 273
// other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead
let UC_ARM64_REG_TTBR0_EL1 = 274
let UC_ARM64_REG_TTBR1_EL1 = 275
let UC_ARM64_REG_ESR_EL0 = 276
let UC_ARM64_REG_ESR_EL1 = 277
let UC_ARM64_REG_ESR_EL2 = 278
let UC_ARM64_REG_ESR_EL3 = 279
let UC_ARM64_REG_FAR_EL0 = 280
let UC_ARM64_REG_FAR_EL1 = 281
let UC_ARM64_REG_FAR_EL2 = 282
let UC_ARM64_REG_FAR_EL3 = 283
let UC_ARM64_REG_PAR_EL1 = 284
let UC_ARM64_REG_MAIR_EL1 = 285
let UC_ARM64_REG_VBAR_EL0 = 286
let UC_ARM64_REG_VBAR_EL1 = 287
let UC_ARM64_REG_VBAR_EL2 = 288
let UC_ARM64_REG_VBAR_EL3 = 289
let UC_ARM64_REG_CP_REG = 290
// floating point control and status registers
let UC_ARM64_REG_FPCR = 291
let UC_ARM64_REG_FPSR = 292
let UC_ARM64_REG_ENDING = 293
// alias registers
let UC_ARM64_REG_IP0 = 215
let UC_ARM64_REG_IP1 = 216
let UC_ARM64_REG_FP = 1
let UC_ARM64_REG_LR = 2
// ARM64 instructions
let UC_ARM64_INS_INVALID = 0
let UC_ARM64_INS_MRS = 1
let UC_ARM64_INS_MSR = 2
let UC_ARM64_INS_SYS = 3
let UC_ARM64_INS_SYSL = 4
let UC_ARM64_INS_ENDING = 5

148
bindings/dotnet/UnicornEngine/Const/Common.fs Normal file
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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
namespace UnicornEngine.Const
open System
[<AutoOpen>]
module Common =
let UC_API_MAJOR = 2
let UC_API_MINOR = 0
let UC_API_PATCH = 1
let UC_API_EXTRA = 255
let UC_VERSION_MAJOR = 2
let UC_VERSION_MINOR = 0
let UC_VERSION_PATCH = 1
let UC_VERSION_EXTRA = 255
let UC_SECOND_SCALE = 1000000
let UC_MILISECOND_SCALE = 1000
let UC_ARCH_ARM = 1
let UC_ARCH_ARM64 = 2
let UC_ARCH_MIPS = 3
let UC_ARCH_X86 = 4
let UC_ARCH_PPC = 5
let UC_ARCH_SPARC = 6
let UC_ARCH_M68K = 7
let UC_ARCH_RISCV = 8
let UC_ARCH_S390X = 9
let UC_ARCH_TRICORE = 10
let UC_ARCH_MAX = 11
let UC_MODE_LITTLE_ENDIAN = 0
let UC_MODE_BIG_ENDIAN = 1073741824
let UC_MODE_ARM = 0
let UC_MODE_THUMB = 16
let UC_MODE_MCLASS = 32
let UC_MODE_V8 = 64
let UC_MODE_ARMBE8 = 1024
let UC_MODE_ARM926 = 128
let UC_MODE_ARM946 = 256
let UC_MODE_ARM1176 = 512
let UC_MODE_MICRO = 16
let UC_MODE_MIPS3 = 32
let UC_MODE_MIPS32R6 = 64
let UC_MODE_MIPS32 = 4
let UC_MODE_MIPS64 = 8
let UC_MODE_16 = 2
let UC_MODE_32 = 4
let UC_MODE_64 = 8
let UC_MODE_PPC32 = 4
let UC_MODE_PPC64 = 8
let UC_MODE_QPX = 16
let UC_MODE_SPARC32 = 4
let UC_MODE_SPARC64 = 8
let UC_MODE_V9 = 16
let UC_MODE_RISCV32 = 4
let UC_MODE_RISCV64 = 8
let UC_ERR_OK = 0
let UC_ERR_NOMEM = 1
let UC_ERR_ARCH = 2
let UC_ERR_HANDLE = 3
let UC_ERR_MODE = 4
let UC_ERR_VERSION = 5
let UC_ERR_READ_UNMAPPED = 6
let UC_ERR_WRITE_UNMAPPED = 7
let UC_ERR_FETCH_UNMAPPED = 8
let UC_ERR_HOOK = 9
let UC_ERR_INSN_INVALID = 10
let UC_ERR_MAP = 11
let UC_ERR_WRITE_PROT = 12
let UC_ERR_READ_PROT = 13
let UC_ERR_FETCH_PROT = 14
let UC_ERR_ARG = 15
let UC_ERR_READ_UNALIGNED = 16
let UC_ERR_WRITE_UNALIGNED = 17
let UC_ERR_FETCH_UNALIGNED = 18
let UC_ERR_HOOK_EXIST = 19
let UC_ERR_RESOURCE = 20
let UC_ERR_EXCEPTION = 21
let UC_MEM_READ = 16
let UC_MEM_WRITE = 17
let UC_MEM_FETCH = 18
let UC_MEM_READ_UNMAPPED = 19
let UC_MEM_WRITE_UNMAPPED = 20
let UC_MEM_FETCH_UNMAPPED = 21
let UC_MEM_WRITE_PROT = 22
let UC_MEM_READ_PROT = 23
let UC_MEM_FETCH_PROT = 24
let UC_MEM_READ_AFTER = 25
let UC_TCG_OP_SUB = 0
let UC_TCG_OP_FLAG_CMP = 1
let UC_TCG_OP_FLAG_DIRECT = 2
let UC_HOOK_INTR = 1
let UC_HOOK_INSN = 2
let UC_HOOK_CODE = 4
let UC_HOOK_BLOCK = 8
let UC_HOOK_MEM_READ_UNMAPPED = 16
let UC_HOOK_MEM_WRITE_UNMAPPED = 32
let UC_HOOK_MEM_FETCH_UNMAPPED = 64
let UC_HOOK_MEM_READ_PROT = 128
let UC_HOOK_MEM_WRITE_PROT = 256
let UC_HOOK_MEM_FETCH_PROT = 512
let UC_HOOK_MEM_READ = 1024
let UC_HOOK_MEM_WRITE = 2048
let UC_HOOK_MEM_FETCH = 4096
let UC_HOOK_MEM_READ_AFTER = 8192
let UC_HOOK_INSN_INVALID = 16384
let UC_HOOK_EDGE_GENERATED = 32768
let UC_HOOK_TCG_OPCODE = 65536
let UC_HOOK_MEM_UNMAPPED = 112
let UC_HOOK_MEM_PROT = 896
let UC_HOOK_MEM_READ_INVALID = 144
let UC_HOOK_MEM_WRITE_INVALID = 288
let UC_HOOK_MEM_FETCH_INVALID = 576
let UC_HOOK_MEM_INVALID = 1008
let UC_HOOK_MEM_VALID = 7168
let UC_QUERY_MODE = 1
let UC_QUERY_PAGE_SIZE = 2
let UC_QUERY_ARCH = 3
let UC_QUERY_TIMEOUT = 4
let UC_CTL_IO_NONE = 0
let UC_CTL_IO_WRITE = 1
let UC_CTL_IO_READ = 2
let UC_CTL_IO_READ_WRITE = 3
let UC_CTL_UC_MODE = 0
let UC_CTL_UC_PAGE_SIZE = 1
let UC_CTL_UC_ARCH = 2
let UC_CTL_UC_TIMEOUT = 3
let UC_CTL_UC_USE_EXITS = 4
let UC_CTL_UC_EXITS_CNT = 5
let UC_CTL_UC_EXITS = 6
let UC_CTL_CPU_MODEL = 7
let UC_CTL_TB_REQUEST_CACHE = 8
let UC_CTL_TB_REMOVE_CACHE = 9
let UC_CTL_TB_FLUSH = 10
let UC_PROT_NONE = 0
let UC_PROT_READ = 1
let UC_PROT_WRITE = 2
let UC_PROT_EXEC = 4
let UC_PROT_ALL = 7

45
bindings/dotnet/UnicornEngine/Const/M68k.fs Normal file
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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
namespace UnicornEngine.Const
open System
[<AutoOpen>]
module M68k =
// M68K CPU
let UC_CPU_M68K_M5206 = 0
let UC_CPU_M68K_M68000 = 1
let UC_CPU_M68K_M68020 = 2
let UC_CPU_M68K_M68030 = 3
let UC_CPU_M68K_M68040 = 4
let UC_CPU_M68K_M68060 = 5
let UC_CPU_M68K_M5208 = 6
let UC_CPU_M68K_CFV4E = 7
let UC_CPU_M68K_ANY = 8
let UC_CPU_M68K_ENDING = 9
// M68K registers
let UC_M68K_REG_INVALID = 0
let UC_M68K_REG_A0 = 1
let UC_M68K_REG_A1 = 2
let UC_M68K_REG_A2 = 3
let UC_M68K_REG_A3 = 4
let UC_M68K_REG_A4 = 5
let UC_M68K_REG_A5 = 6
let UC_M68K_REG_A6 = 7
let UC_M68K_REG_A7 = 8
let UC_M68K_REG_D0 = 9
let UC_M68K_REG_D1 = 10
let UC_M68K_REG_D2 = 11
let UC_M68K_REG_D3 = 12
let UC_M68K_REG_D4 = 13
let UC_M68K_REG_D5 = 14
let UC_M68K_REG_D6 = 15
let UC_M68K_REG_D7 = 16
let UC_M68K_REG_SR = 17
let UC_M68K_REG_PC = 18
let UC_M68K_REG_ENDING = 19

243
bindings/dotnet/UnicornEngine/Const/Mips.fs Normal file
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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
namespace UnicornEngine.Const
open System
[<AutoOpen>]
module Mips =
// MIPS32 CPUS
let UC_CPU_MIPS32_4KC = 0
let UC_CPU_MIPS32_4KM = 1
let UC_CPU_MIPS32_4KECR1 = 2
let UC_CPU_MIPS32_4KEMR1 = 3
let UC_CPU_MIPS32_4KEC = 4
let UC_CPU_MIPS32_4KEM = 5
let UC_CPU_MIPS32_24KC = 6
let UC_CPU_MIPS32_24KEC = 7
let UC_CPU_MIPS32_24KF = 8
let UC_CPU_MIPS32_34KF = 9
let UC_CPU_MIPS32_74KF = 10
let UC_CPU_MIPS32_M14K = 11
let UC_CPU_MIPS32_M14KC = 12
let UC_CPU_MIPS32_P5600 = 13
let UC_CPU_MIPS32_MIPS32R6_GENERIC = 14
let UC_CPU_MIPS32_I7200 = 15
let UC_CPU_MIPS32_ENDING = 16
// MIPS64 CPUS
let UC_CPU_MIPS64_R4000 = 0
let UC_CPU_MIPS64_VR5432 = 1
let UC_CPU_MIPS64_5KC = 2
let UC_CPU_MIPS64_5KF = 3
let UC_CPU_MIPS64_20KC = 4
let UC_CPU_MIPS64_MIPS64R2_GENERIC = 5
let UC_CPU_MIPS64_5KEC = 6
let UC_CPU_MIPS64_5KEF = 7
let UC_CPU_MIPS64_I6400 = 8
let UC_CPU_MIPS64_I6500 = 9
let UC_CPU_MIPS64_LOONGSON_2E = 10
let UC_CPU_MIPS64_LOONGSON_2F = 11
let UC_CPU_MIPS64_MIPS64DSPR2 = 12
let UC_CPU_MIPS64_ENDING = 13
// MIPS registers
let UC_MIPS_REG_INVALID = 0
// General purpose registers
let UC_MIPS_REG_PC = 1
let UC_MIPS_REG_0 = 2
let UC_MIPS_REG_1 = 3
let UC_MIPS_REG_2 = 4
let UC_MIPS_REG_3 = 5
let UC_MIPS_REG_4 = 6
let UC_MIPS_REG_5 = 7
let UC_MIPS_REG_6 = 8
let UC_MIPS_REG_7 = 9
let UC_MIPS_REG_8 = 10
let UC_MIPS_REG_9 = 11
let UC_MIPS_REG_10 = 12
let UC_MIPS_REG_11 = 13
let UC_MIPS_REG_12 = 14
let UC_MIPS_REG_13 = 15
let UC_MIPS_REG_14 = 16
let UC_MIPS_REG_15 = 17
let UC_MIPS_REG_16 = 18
let UC_MIPS_REG_17 = 19
let UC_MIPS_REG_18 = 20
let UC_MIPS_REG_19 = 21
let UC_MIPS_REG_20 = 22
let UC_MIPS_REG_21 = 23
let UC_MIPS_REG_22 = 24
let UC_MIPS_REG_23 = 25
let UC_MIPS_REG_24 = 26
let UC_MIPS_REG_25 = 27
let UC_MIPS_REG_26 = 28
let UC_MIPS_REG_27 = 29
let UC_MIPS_REG_28 = 30
let UC_MIPS_REG_29 = 31
let UC_MIPS_REG_30 = 32
let UC_MIPS_REG_31 = 33
// DSP registers
let UC_MIPS_REG_DSPCCOND = 34
let UC_MIPS_REG_DSPCARRY = 35
let UC_MIPS_REG_DSPEFI = 36
let UC_MIPS_REG_DSPOUTFLAG = 37
let UC_MIPS_REG_DSPOUTFLAG16_19 = 38
let UC_MIPS_REG_DSPOUTFLAG20 = 39
let UC_MIPS_REG_DSPOUTFLAG21 = 40
let UC_MIPS_REG_DSPOUTFLAG22 = 41
let UC_MIPS_REG_DSPOUTFLAG23 = 42
let UC_MIPS_REG_DSPPOS = 43
let UC_MIPS_REG_DSPSCOUNT = 44
// ACC registers
let UC_MIPS_REG_AC0 = 45
let UC_MIPS_REG_AC1 = 46
let UC_MIPS_REG_AC2 = 47
let UC_MIPS_REG_AC3 = 48
// COP registers
let UC_MIPS_REG_CC0 = 49
let UC_MIPS_REG_CC1 = 50
let UC_MIPS_REG_CC2 = 51
let UC_MIPS_REG_CC3 = 52
let UC_MIPS_REG_CC4 = 53
let UC_MIPS_REG_CC5 = 54
let UC_MIPS_REG_CC6 = 55
let UC_MIPS_REG_CC7 = 56
// FPU registers
let UC_MIPS_REG_F0 = 57
let UC_MIPS_REG_F1 = 58
let UC_MIPS_REG_F2 = 59
let UC_MIPS_REG_F3 = 60
let UC_MIPS_REG_F4 = 61
let UC_MIPS_REG_F5 = 62
let UC_MIPS_REG_F6 = 63
let UC_MIPS_REG_F7 = 64
let UC_MIPS_REG_F8 = 65
let UC_MIPS_REG_F9 = 66
let UC_MIPS_REG_F10 = 67
let UC_MIPS_REG_F11 = 68
let UC_MIPS_REG_F12 = 69
let UC_MIPS_REG_F13 = 70
let UC_MIPS_REG_F14 = 71
let UC_MIPS_REG_F15 = 72
let UC_MIPS_REG_F16 = 73
let UC_MIPS_REG_F17 = 74
let UC_MIPS_REG_F18 = 75
let UC_MIPS_REG_F19 = 76
let UC_MIPS_REG_F20 = 77
let UC_MIPS_REG_F21 = 78
let UC_MIPS_REG_F22 = 79
let UC_MIPS_REG_F23 = 80
let UC_MIPS_REG_F24 = 81
let UC_MIPS_REG_F25 = 82
let UC_MIPS_REG_F26 = 83
let UC_MIPS_REG_F27 = 84
let UC_MIPS_REG_F28 = 85
let UC_MIPS_REG_F29 = 86
let UC_MIPS_REG_F30 = 87
let UC_MIPS_REG_F31 = 88
let UC_MIPS_REG_FCC0 = 89
let UC_MIPS_REG_FCC1 = 90
let UC_MIPS_REG_FCC2 = 91
let UC_MIPS_REG_FCC3 = 92
let UC_MIPS_REG_FCC4 = 93
let UC_MIPS_REG_FCC5 = 94
let UC_MIPS_REG_FCC6 = 95
let UC_MIPS_REG_FCC7 = 96
// AFPR128
let UC_MIPS_REG_W0 = 97
let UC_MIPS_REG_W1 = 98
let UC_MIPS_REG_W2 = 99
let UC_MIPS_REG_W3 = 100
let UC_MIPS_REG_W4 = 101
let UC_MIPS_REG_W5 = 102
let UC_MIPS_REG_W6 = 103
let UC_MIPS_REG_W7 = 104
let UC_MIPS_REG_W8 = 105
let UC_MIPS_REG_W9 = 106
let UC_MIPS_REG_W10 = 107
let UC_MIPS_REG_W11 = 108
let UC_MIPS_REG_W12 = 109
let UC_MIPS_REG_W13 = 110
let UC_MIPS_REG_W14 = 111
let UC_MIPS_REG_W15 = 112
let UC_MIPS_REG_W16 = 113
let UC_MIPS_REG_W17 = 114
let UC_MIPS_REG_W18 = 115
let UC_MIPS_REG_W19 = 116
let UC_MIPS_REG_W20 = 117
let UC_MIPS_REG_W21 = 118
let UC_MIPS_REG_W22 = 119
let UC_MIPS_REG_W23 = 120
let UC_MIPS_REG_W24 = 121
let UC_MIPS_REG_W25 = 122
let UC_MIPS_REG_W26 = 123
let UC_MIPS_REG_W27 = 124
let UC_MIPS_REG_W28 = 125
let UC_MIPS_REG_W29 = 126
let UC_MIPS_REG_W30 = 127
let UC_MIPS_REG_W31 = 128
let UC_MIPS_REG_HI = 129
let UC_MIPS_REG_LO = 130
let UC_MIPS_REG_P0 = 131
let UC_MIPS_REG_P1 = 132
let UC_MIPS_REG_P2 = 133
let UC_MIPS_REG_MPL0 = 134
let UC_MIPS_REG_MPL1 = 135
let UC_MIPS_REG_MPL2 = 136
let UC_MIPS_REG_CP0_CONFIG3 = 137
let UC_MIPS_REG_CP0_USERLOCAL = 138
let UC_MIPS_REG_CP0_STATUS = 139
let UC_MIPS_REG_ENDING = 140
let UC_MIPS_REG_ZERO = 2
let UC_MIPS_REG_AT = 3
let UC_MIPS_REG_V0 = 4
let UC_MIPS_REG_V1 = 5
let UC_MIPS_REG_A0 = 6
let UC_MIPS_REG_A1 = 7
let UC_MIPS_REG_A2 = 8
let UC_MIPS_REG_A3 = 9
let UC_MIPS_REG_T0 = 10
let UC_MIPS_REG_T1 = 11
let UC_MIPS_REG_T2 = 12
let UC_MIPS_REG_T3 = 13
let UC_MIPS_REG_T4 = 14
let UC_MIPS_REG_T5 = 15
let UC_MIPS_REG_T6 = 16
let UC_MIPS_REG_T7 = 17
let UC_MIPS_REG_S0 = 18
let UC_MIPS_REG_S1 = 19
let UC_MIPS_REG_S2 = 20
let UC_MIPS_REG_S3 = 21
let UC_MIPS_REG_S4 = 22
let UC_MIPS_REG_S5 = 23
let UC_MIPS_REG_S6 = 24
let UC_MIPS_REG_S7 = 25
let UC_MIPS_REG_T8 = 26
let UC_MIPS_REG_T9 = 27
let UC_MIPS_REG_K0 = 28
let UC_MIPS_REG_K1 = 29
let UC_MIPS_REG_GP = 30
let UC_MIPS_REG_SP = 31
let UC_MIPS_REG_FP = 32
let UC_MIPS_REG_S8 = 32
let UC_MIPS_REG_RA = 33
let UC_MIPS_REG_HI0 = 45
let UC_MIPS_REG_HI1 = 46
let UC_MIPS_REG_HI2 = 47
let UC_MIPS_REG_HI3 = 48
let UC_MIPS_REG_LO0 = 45
let UC_MIPS_REG_LO1 = 46
let UC_MIPS_REG_LO2 = 47
let UC_MIPS_REG_LO3 = 48

412
bindings/dotnet/UnicornEngine/Const/Ppc.fs Normal file
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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
namespace UnicornEngine.Const
open System
[<AutoOpen>]
module Ppc =
// PPC CPU
let UC_CPU_PPC32_401 = 0
let UC_CPU_PPC32_401A1 = 1
let UC_CPU_PPC32_401B2 = 2
let UC_CPU_PPC32_401C2 = 3
let UC_CPU_PPC32_401D2 = 4
let UC_CPU_PPC32_401E2 = 5
let UC_CPU_PPC32_401F2 = 6
let UC_CPU_PPC32_401G2 = 7
let UC_CPU_PPC32_IOP480 = 8
let UC_CPU_PPC32_COBRA = 9
let UC_CPU_PPC32_403GA = 10
let UC_CPU_PPC32_403GB = 11
let UC_CPU_PPC32_403GC = 12
let UC_CPU_PPC32_403GCX = 13
let UC_CPU_PPC32_405D2 = 14
let UC_CPU_PPC32_405D4 = 15
let UC_CPU_PPC32_405CRA = 16
let UC_CPU_PPC32_405CRB = 17
let UC_CPU_PPC32_405CRC = 18
let UC_CPU_PPC32_405EP = 19
let UC_CPU_PPC32_405EZ = 20
let UC_CPU_PPC32_405GPA = 21
let UC_CPU_PPC32_405GPB = 22
let UC_CPU_PPC32_405GPC = 23
let UC_CPU_PPC32_405GPD = 24
let UC_CPU_PPC32_405GPR = 25
let UC_CPU_PPC32_405LP = 26
let UC_CPU_PPC32_NPE405H = 27
let UC_CPU_PPC32_NPE405H2 = 28
let UC_CPU_PPC32_NPE405L = 29
let UC_CPU_PPC32_NPE4GS3 = 30
let UC_CPU_PPC32_STB03 = 31
let UC_CPU_PPC32_STB04 = 32
let UC_CPU_PPC32_STB25 = 33
let UC_CPU_PPC32_X2VP4 = 34
let UC_CPU_PPC32_X2VP20 = 35
let UC_CPU_PPC32_440_XILINX = 36
let UC_CPU_PPC32_440_XILINX_W_DFPU = 37
let UC_CPU_PPC32_440EPA = 38
let UC_CPU_PPC32_440EPB = 39
let UC_CPU_PPC32_440EPX = 40
let UC_CPU_PPC32_460EXB = 41
let UC_CPU_PPC32_G2 = 42
let UC_CPU_PPC32_G2H4 = 43
let UC_CPU_PPC32_G2GP = 44
let UC_CPU_PPC32_G2LS = 45
let UC_CPU_PPC32_G2HIP3 = 46
let UC_CPU_PPC32_G2HIP4 = 47
let UC_CPU_PPC32_MPC603 = 48
let UC_CPU_PPC32_G2LE = 49
let UC_CPU_PPC32_G2LEGP = 50
let UC_CPU_PPC32_G2LELS = 51
let UC_CPU_PPC32_G2LEGP1 = 52
let UC_CPU_PPC32_G2LEGP3 = 53
let UC_CPU_PPC32_MPC5200_V10 = 54
let UC_CPU_PPC32_MPC5200_V11 = 55
let UC_CPU_PPC32_MPC5200_V12 = 56
let UC_CPU_PPC32_MPC5200B_V20 = 57
let UC_CPU_PPC32_MPC5200B_V21 = 58
let UC_CPU_PPC32_E200Z5 = 59
let UC_CPU_PPC32_E200Z6 = 60
let UC_CPU_PPC32_E300C1 = 61
let UC_CPU_PPC32_E300C2 = 62
let UC_CPU_PPC32_E300C3 = 63
let UC_CPU_PPC32_E300C4 = 64
let UC_CPU_PPC32_MPC8343 = 65
let UC_CPU_PPC32_MPC8343A = 66
let UC_CPU_PPC32_MPC8343E = 67
let UC_CPU_PPC32_MPC8343EA = 68
let UC_CPU_PPC32_MPC8347T = 69
let UC_CPU_PPC32_MPC8347P = 70
let UC_CPU_PPC32_MPC8347AT = 71
let UC_CPU_PPC32_MPC8347AP = 72
let UC_CPU_PPC32_MPC8347ET = 73
let UC_CPU_PPC32_MPC8347EP = 74
let UC_CPU_PPC32_MPC8347EAT = 75
let UC_CPU_PPC32_MPC8347EAP = 76
let UC_CPU_PPC32_MPC8349 = 77
let UC_CPU_PPC32_MPC8349A = 78
let UC_CPU_PPC32_MPC8349E = 79
let UC_CPU_PPC32_MPC8349EA = 80
let UC_CPU_PPC32_MPC8377 = 81
let UC_CPU_PPC32_MPC8377E = 82
let UC_CPU_PPC32_MPC8378 = 83
let UC_CPU_PPC32_MPC8378E = 84
let UC_CPU_PPC32_MPC8379 = 85
let UC_CPU_PPC32_MPC8379E = 86
let UC_CPU_PPC32_E500_V10 = 87
let UC_CPU_PPC32_E500_V20 = 88
let UC_CPU_PPC32_E500V2_V10 = 89
let UC_CPU_PPC32_E500V2_V20 = 90
let UC_CPU_PPC32_E500V2_V21 = 91
let UC_CPU_PPC32_E500V2_V22 = 92
let UC_CPU_PPC32_E500V2_V30 = 93
let UC_CPU_PPC32_E500MC = 94
let UC_CPU_PPC32_MPC8533_V10 = 95
let UC_CPU_PPC32_MPC8533_V11 = 96
let UC_CPU_PPC32_MPC8533E_V10 = 97
let UC_CPU_PPC32_MPC8533E_V11 = 98
let UC_CPU_PPC32_MPC8540_V10 = 99
let UC_CPU_PPC32_MPC8540_V20 = 100
let UC_CPU_PPC32_MPC8540_V21 = 101
let UC_CPU_PPC32_MPC8541_V10 = 102
let UC_CPU_PPC32_MPC8541_V11 = 103
let UC_CPU_PPC32_MPC8541E_V10 = 104
let UC_CPU_PPC32_MPC8541E_V11 = 105
let UC_CPU_PPC32_MPC8543_V10 = 106
let UC_CPU_PPC32_MPC8543_V11 = 107
let UC_CPU_PPC32_MPC8543_V20 = 108
let UC_CPU_PPC32_MPC8543_V21 = 109
let UC_CPU_PPC32_MPC8543E_V10 = 110
let UC_CPU_PPC32_MPC8543E_V11 = 111
let UC_CPU_PPC32_MPC8543E_V20 = 112
let UC_CPU_PPC32_MPC8543E_V21 = 113
let UC_CPU_PPC32_MPC8544_V10 = 114
let UC_CPU_PPC32_MPC8544_V11 = 115
let UC_CPU_PPC32_MPC8544E_V10 = 116
let UC_CPU_PPC32_MPC8544E_V11 = 117
let UC_CPU_PPC32_MPC8545_V20 = 118
let UC_CPU_PPC32_MPC8545_V21 = 119
let UC_CPU_PPC32_MPC8545E_V20 = 120
let UC_CPU_PPC32_MPC8545E_V21 = 121
let UC_CPU_PPC32_MPC8547E_V20 = 122
let UC_CPU_PPC32_MPC8547E_V21 = 123
let UC_CPU_PPC32_MPC8548_V10 = 124
let UC_CPU_PPC32_MPC8548_V11 = 125
let UC_CPU_PPC32_MPC8548_V20 = 126
let UC_CPU_PPC32_MPC8548_V21 = 127
let UC_CPU_PPC32_MPC8548E_V10 = 128
let UC_CPU_PPC32_MPC8548E_V11 = 129
let UC_CPU_PPC32_MPC8548E_V20 = 130
let UC_CPU_PPC32_MPC8548E_V21 = 131
let UC_CPU_PPC32_MPC8555_V10 = 132
let UC_CPU_PPC32_MPC8555_V11 = 133
let UC_CPU_PPC32_MPC8555E_V10 = 134
let UC_CPU_PPC32_MPC8555E_V11 = 135
let UC_CPU_PPC32_MPC8560_V10 = 136
let UC_CPU_PPC32_MPC8560_V20 = 137
let UC_CPU_PPC32_MPC8560_V21 = 138
let UC_CPU_PPC32_MPC8567 = 139
let UC_CPU_PPC32_MPC8567E = 140
let UC_CPU_PPC32_MPC8568 = 141
let UC_CPU_PPC32_MPC8568E = 142
let UC_CPU_PPC32_MPC8572 = 143
let UC_CPU_PPC32_MPC8572E = 144
let UC_CPU_PPC32_E600 = 145
let UC_CPU_PPC32_MPC8610 = 146
let UC_CPU_PPC32_MPC8641 = 147
let UC_CPU_PPC32_MPC8641D = 148
let UC_CPU_PPC32_601_V0 = 149
let UC_CPU_PPC32_601_V1 = 150
let UC_CPU_PPC32_601_V2 = 151
let UC_CPU_PPC32_602 = 152
let UC_CPU_PPC32_603 = 153
let UC_CPU_PPC32_603E_V1_1 = 154
let UC_CPU_PPC32_603E_V1_2 = 155
let UC_CPU_PPC32_603E_V1_3 = 156
let UC_CPU_PPC32_603E_V1_4 = 157
let UC_CPU_PPC32_603E_V2_2 = 158
let UC_CPU_PPC32_603E_V3 = 159
let UC_CPU_PPC32_603E_V4 = 160
let UC_CPU_PPC32_603E_V4_1 = 161
let UC_CPU_PPC32_603E7 = 162
let UC_CPU_PPC32_603E7T = 163
let UC_CPU_PPC32_603E7V = 164
let UC_CPU_PPC32_603E7V1 = 165
let UC_CPU_PPC32_603E7V2 = 166
let UC_CPU_PPC32_603P = 167
let UC_CPU_PPC32_604 = 168
let UC_CPU_PPC32_604E_V1_0 = 169
let UC_CPU_PPC32_604E_V2_2 = 170
let UC_CPU_PPC32_604E_V2_4 = 171
let UC_CPU_PPC32_604R = 172
let UC_CPU_PPC32_740_V1_0 = 173
let UC_CPU_PPC32_750_V1_0 = 174
let UC_CPU_PPC32_740_V2_0 = 175
let UC_CPU_PPC32_750_V2_0 = 176
let UC_CPU_PPC32_740_V2_1 = 177
let UC_CPU_PPC32_750_V2_1 = 178
let UC_CPU_PPC32_740_V2_2 = 179
let UC_CPU_PPC32_750_V2_2 = 180
let UC_CPU_PPC32_740_V3_0 = 181
let UC_CPU_PPC32_750_V3_0 = 182
let UC_CPU_PPC32_740_V3_1 = 183
let UC_CPU_PPC32_750_V3_1 = 184
let UC_CPU_PPC32_740E = 185
let UC_CPU_PPC32_750E = 186
let UC_CPU_PPC32_740P = 187
let UC_CPU_PPC32_750P = 188
let UC_CPU_PPC32_750CL_V1_0 = 189
let UC_CPU_PPC32_750CL_V2_0 = 190
let UC_CPU_PPC32_750CX_V1_0 = 191
let UC_CPU_PPC32_750CX_V2_0 = 192
let UC_CPU_PPC32_750CX_V2_1 = 193
let UC_CPU_PPC32_750CX_V2_2 = 194
let UC_CPU_PPC32_750CXE_V2_1 = 195
let UC_CPU_PPC32_750CXE_V2_2 = 196
let UC_CPU_PPC32_750CXE_V2_3 = 197
let UC_CPU_PPC32_750CXE_V2_4 = 198
let UC_CPU_PPC32_750CXE_V2_4B = 199
let UC_CPU_PPC32_750CXE_V3_0 = 200
let UC_CPU_PPC32_750CXE_V3_1 = 201
let UC_CPU_PPC32_750CXE_V3_1B = 202
let UC_CPU_PPC32_750CXR = 203
let UC_CPU_PPC32_750FL = 204
let UC_CPU_PPC32_750FX_V1_0 = 205
let UC_CPU_PPC32_750FX_V2_0 = 206
let UC_CPU_PPC32_750FX_V2_1 = 207
let UC_CPU_PPC32_750FX_V2_2 = 208
let UC_CPU_PPC32_750FX_V2_3 = 209
let UC_CPU_PPC32_750GL = 210
let UC_CPU_PPC32_750GX_V1_0 = 211
let UC_CPU_PPC32_750GX_V1_1 = 212
let UC_CPU_PPC32_750GX_V1_2 = 213
let UC_CPU_PPC32_750L_V2_0 = 214
let UC_CPU_PPC32_750L_V2_1 = 215
let UC_CPU_PPC32_750L_V2_2 = 216
let UC_CPU_PPC32_750L_V3_0 = 217
let UC_CPU_PPC32_750L_V3_2 = 218
let UC_CPU_PPC32_745_V1_0 = 219
let UC_CPU_PPC32_755_V1_0 = 220
let UC_CPU_PPC32_745_V1_1 = 221
let UC_CPU_PPC32_755_V1_1 = 222
let UC_CPU_PPC32_745_V2_0 = 223
let UC_CPU_PPC32_755_V2_0 = 224
let UC_CPU_PPC32_745_V2_1 = 225
let UC_CPU_PPC32_755_V2_1 = 226
let UC_CPU_PPC32_745_V2_2 = 227
let UC_CPU_PPC32_755_V2_2 = 228
let UC_CPU_PPC32_745_V2_3 = 229
let UC_CPU_PPC32_755_V2_3 = 230
let UC_CPU_PPC32_745_V2_4 = 231
let UC_CPU_PPC32_755_V2_4 = 232
let UC_CPU_PPC32_745_V2_5 = 233
let UC_CPU_PPC32_755_V2_5 = 234
let UC_CPU_PPC32_745_V2_6 = 235
let UC_CPU_PPC32_755_V2_6 = 236
let UC_CPU_PPC32_745_V2_7 = 237
let UC_CPU_PPC32_755_V2_7 = 238
let UC_CPU_PPC32_745_V2_8 = 239
let UC_CPU_PPC32_755_V2_8 = 240
let UC_CPU_PPC32_7400_V1_0 = 241
let UC_CPU_PPC32_7400_V1_1 = 242
let UC_CPU_PPC32_7400_V2_0 = 243
let UC_CPU_PPC32_7400_V2_1 = 244
let UC_CPU_PPC32_7400_V2_2 = 245
let UC_CPU_PPC32_7400_V2_6 = 246
let UC_CPU_PPC32_7400_V2_7 = 247
let UC_CPU_PPC32_7400_V2_8 = 248
let UC_CPU_PPC32_7400_V2_9 = 249
let UC_CPU_PPC32_7410_V1_0 = 250
let UC_CPU_PPC32_7410_V1_1 = 251
let UC_CPU_PPC32_7410_V1_2 = 252
let UC_CPU_PPC32_7410_V1_3 = 253
let UC_CPU_PPC32_7410_V1_4 = 254
let UC_CPU_PPC32_7448_V1_0 = 255
let UC_CPU_PPC32_7448_V1_1 = 256
let UC_CPU_PPC32_7448_V2_0 = 257
let UC_CPU_PPC32_7448_V2_1 = 258
let UC_CPU_PPC32_7450_V1_0 = 259
let UC_CPU_PPC32_7450_V1_1 = 260
let UC_CPU_PPC32_7450_V1_2 = 261
let UC_CPU_PPC32_7450_V2_0 = 262
let UC_CPU_PPC32_7450_V2_1 = 263
let UC_CPU_PPC32_7441_V2_1 = 264
let UC_CPU_PPC32_7441_V2_3 = 265
let UC_CPU_PPC32_7451_V2_3 = 266
let UC_CPU_PPC32_7441_V2_10 = 267
let UC_CPU_PPC32_7451_V2_10 = 268
let UC_CPU_PPC32_7445_V1_0 = 269
let UC_CPU_PPC32_7455_V1_0 = 270
let UC_CPU_PPC32_7445_V2_1 = 271
let UC_CPU_PPC32_7455_V2_1 = 272
let UC_CPU_PPC32_7445_V3_2 = 273
let UC_CPU_PPC32_7455_V3_2 = 274
let UC_CPU_PPC32_7445_V3_3 = 275
let UC_CPU_PPC32_7455_V3_3 = 276
let UC_CPU_PPC32_7445_V3_4 = 277
let UC_CPU_PPC32_7455_V3_4 = 278
let UC_CPU_PPC32_7447_V1_0 = 279
let UC_CPU_PPC32_7457_V1_0 = 280
let UC_CPU_PPC32_7447_V1_1 = 281
let UC_CPU_PPC32_7457_V1_1 = 282
let UC_CPU_PPC32_7457_V1_2 = 283
let UC_CPU_PPC32_7447A_V1_0 = 284
let UC_CPU_PPC32_7457A_V1_0 = 285
let UC_CPU_PPC32_7447A_V1_1 = 286
let UC_CPU_PPC32_7457A_V1_1 = 287
let UC_CPU_PPC32_7447A_V1_2 = 288
let UC_CPU_PPC32_7457A_V1_2 = 289
let UC_CPU_PPC32_ENDING = 290
// PPC64 CPU
let UC_CPU_PPC64_E5500 = 0
let UC_CPU_PPC64_E6500 = 1
let UC_CPU_PPC64_970_V2_2 = 2
let UC_CPU_PPC64_970FX_V1_0 = 3
let UC_CPU_PPC64_970FX_V2_0 = 4
let UC_CPU_PPC64_970FX_V2_1 = 5
let UC_CPU_PPC64_970FX_V3_0 = 6
let UC_CPU_PPC64_970FX_V3_1 = 7
let UC_CPU_PPC64_970MP_V1_0 = 8
let UC_CPU_PPC64_970MP_V1_1 = 9
let UC_CPU_PPC64_POWER5_V2_1 = 10
let UC_CPU_PPC64_POWER7_V2_3 = 11
let UC_CPU_PPC64_POWER7_V2_1 = 12
let UC_CPU_PPC64_POWER8E_V2_1 = 13
let UC_CPU_PPC64_POWER8_V2_0 = 14
let UC_CPU_PPC64_POWER8NVL_V1_0 = 15
let UC_CPU_PPC64_POWER9_V1_0 = 16
let UC_CPU_PPC64_POWER9_V2_0 = 17
let UC_CPU_PPC64_POWER10_V1_0 = 18
let UC_CPU_PPC64_ENDING = 19
// PPC registers
let UC_PPC_REG_INVALID = 0
// General purpose registers
let UC_PPC_REG_PC = 1
let UC_PPC_REG_0 = 2
let UC_PPC_REG_1 = 3
let UC_PPC_REG_2 = 4
let UC_PPC_REG_3 = 5
let UC_PPC_REG_4 = 6
let UC_PPC_REG_5 = 7
let UC_PPC_REG_6 = 8
let UC_PPC_REG_7 = 9
let UC_PPC_REG_8 = 10
let UC_PPC_REG_9 = 11
let UC_PPC_REG_10 = 12
let UC_PPC_REG_11 = 13
let UC_PPC_REG_12 = 14
let UC_PPC_REG_13 = 15
let UC_PPC_REG_14 = 16
let UC_PPC_REG_15 = 17
let UC_PPC_REG_16 = 18
let UC_PPC_REG_17 = 19
let UC_PPC_REG_18 = 20
let UC_PPC_REG_19 = 21
let UC_PPC_REG_20 = 22
let UC_PPC_REG_21 = 23
let UC_PPC_REG_22 = 24
let UC_PPC_REG_23 = 25
let UC_PPC_REG_24 = 26
let UC_PPC_REG_25 = 27
let UC_PPC_REG_26 = 28
let UC_PPC_REG_27 = 29
let UC_PPC_REG_28 = 30
let UC_PPC_REG_29 = 31
let UC_PPC_REG_30 = 32
let UC_PPC_REG_31 = 33
let UC_PPC_REG_CR0 = 34
let UC_PPC_REG_CR1 = 35
let UC_PPC_REG_CR2 = 36
let UC_PPC_REG_CR3 = 37
let UC_PPC_REG_CR4 = 38
let UC_PPC_REG_CR5 = 39
let UC_PPC_REG_CR6 = 40
let UC_PPC_REG_CR7 = 41
let UC_PPC_REG_FPR0 = 42
let UC_PPC_REG_FPR1 = 43
let UC_PPC_REG_FPR2 = 44
let UC_PPC_REG_FPR3 = 45
let UC_PPC_REG_FPR4 = 46
let UC_PPC_REG_FPR5 = 47
let UC_PPC_REG_FPR6 = 48
let UC_PPC_REG_FPR7 = 49
let UC_PPC_REG_FPR8 = 50
let UC_PPC_REG_FPR9 = 51
let UC_PPC_REG_FPR10 = 52
let UC_PPC_REG_FPR11 = 53
let UC_PPC_REG_FPR12 = 54
let UC_PPC_REG_FPR13 = 55
let UC_PPC_REG_FPR14 = 56
let UC_PPC_REG_FPR15 = 57
let UC_PPC_REG_FPR16 = 58
let UC_PPC_REG_FPR17 = 59
let UC_PPC_REG_FPR18 = 60
let UC_PPC_REG_FPR19 = 61
let UC_PPC_REG_FPR20 = 62
let UC_PPC_REG_FPR21 = 63
let UC_PPC_REG_FPR22 = 64
let UC_PPC_REG_FPR23 = 65
let UC_PPC_REG_FPR24 = 66
let UC_PPC_REG_FPR25 = 67
let UC_PPC_REG_FPR26 = 68
let UC_PPC_REG_FPR27 = 69
let UC_PPC_REG_FPR28 = 70
let UC_PPC_REG_FPR29 = 71
let UC_PPC_REG_FPR30 = 72
let UC_PPC_REG_FPR31 = 73
let UC_PPC_REG_LR = 74
let UC_PPC_REG_XER = 75
let UC_PPC_REG_CTR = 76
let UC_PPC_REG_MSR = 77
let UC_PPC_REG_FPSCR = 78
let UC_PPC_REG_CR = 79
let UC_PPC_REG_ENDING = 80

293
bindings/dotnet/UnicornEngine/Const/Riscv.fs Normal file
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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
namespace UnicornEngine.Const
open System
[<AutoOpen>]
module Riscv =
// RISCV32 CPU
let UC_CPU_RISCV32_ANY = 0
let UC_CPU_RISCV32_BASE32 = 1
let UC_CPU_RISCV32_SIFIVE_E31 = 2
let UC_CPU_RISCV32_SIFIVE_U34 = 3
let UC_CPU_RISCV32_ENDING = 4
// RISCV64 CPU
let UC_CPU_RISCV64_ANY = 0
let UC_CPU_RISCV64_BASE64 = 1
let UC_CPU_RISCV64_SIFIVE_E51 = 2
let UC_CPU_RISCV64_SIFIVE_U54 = 3
let UC_CPU_RISCV64_ENDING = 4
// RISCV registers
let UC_RISCV_REG_INVALID = 0
// General purpose registers
let UC_RISCV_REG_X0 = 1
let UC_RISCV_REG_X1 = 2
let UC_RISCV_REG_X2 = 3
let UC_RISCV_REG_X3 = 4
let UC_RISCV_REG_X4 = 5
let UC_RISCV_REG_X5 = 6
let UC_RISCV_REG_X6 = 7
let UC_RISCV_REG_X7 = 8
let UC_RISCV_REG_X8 = 9
let UC_RISCV_REG_X9 = 10
let UC_RISCV_REG_X10 = 11
let UC_RISCV_REG_X11 = 12
let UC_RISCV_REG_X12 = 13
let UC_RISCV_REG_X13 = 14
let UC_RISCV_REG_X14 = 15
let UC_RISCV_REG_X15 = 16
let UC_RISCV_REG_X16 = 17
let UC_RISCV_REG_X17 = 18
let UC_RISCV_REG_X18 = 19
let UC_RISCV_REG_X19 = 20
let UC_RISCV_REG_X20 = 21
let UC_RISCV_REG_X21 = 22
let UC_RISCV_REG_X22 = 23
let UC_RISCV_REG_X23 = 24
let UC_RISCV_REG_X24 = 25
let UC_RISCV_REG_X25 = 26
let UC_RISCV_REG_X26 = 27
let UC_RISCV_REG_X27 = 28
let UC_RISCV_REG_X28 = 29
let UC_RISCV_REG_X29 = 30
let UC_RISCV_REG_X30 = 31
let UC_RISCV_REG_X31 = 32
// RISCV CSR
let UC_RISCV_REG_USTATUS = 33
let UC_RISCV_REG_UIE = 34
let UC_RISCV_REG_UTVEC = 35
let UC_RISCV_REG_USCRATCH = 36
let UC_RISCV_REG_UEPC = 37
let UC_RISCV_REG_UCAUSE = 38
let UC_RISCV_REG_UTVAL = 39
let UC_RISCV_REG_UIP = 40
let UC_RISCV_REG_FFLAGS = 41
let UC_RISCV_REG_FRM = 42
let UC_RISCV_REG_FCSR = 43
let UC_RISCV_REG_CYCLE = 44
let UC_RISCV_REG_TIME = 45
let UC_RISCV_REG_INSTRET = 46
let UC_RISCV_REG_HPMCOUNTER3 = 47
let UC_RISCV_REG_HPMCOUNTER4 = 48
let UC_RISCV_REG_HPMCOUNTER5 = 49
let UC_RISCV_REG_HPMCOUNTER6 = 50
let UC_RISCV_REG_HPMCOUNTER7 = 51
let UC_RISCV_REG_HPMCOUNTER8 = 52
let UC_RISCV_REG_HPMCOUNTER9 = 53
let UC_RISCV_REG_HPMCOUNTER10 = 54
let UC_RISCV_REG_HPMCOUNTER11 = 55
let UC_RISCV_REG_HPMCOUNTER12 = 56
let UC_RISCV_REG_HPMCOUNTER13 = 57
let UC_RISCV_REG_HPMCOUNTER14 = 58
let UC_RISCV_REG_HPMCOUNTER15 = 59
let UC_RISCV_REG_HPMCOUNTER16 = 60
let UC_RISCV_REG_HPMCOUNTER17 = 61
let UC_RISCV_REG_HPMCOUNTER18 = 62
let UC_RISCV_REG_HPMCOUNTER19 = 63
let UC_RISCV_REG_HPMCOUNTER20 = 64
let UC_RISCV_REG_HPMCOUNTER21 = 65
let UC_RISCV_REG_HPMCOUNTER22 = 66
let UC_RISCV_REG_HPMCOUNTER23 = 67
let UC_RISCV_REG_HPMCOUNTER24 = 68
let UC_RISCV_REG_HPMCOUNTER25 = 69
let UC_RISCV_REG_HPMCOUNTER26 = 70
let UC_RISCV_REG_HPMCOUNTER27 = 71
let UC_RISCV_REG_HPMCOUNTER28 = 72
let UC_RISCV_REG_HPMCOUNTER29 = 73
let UC_RISCV_REG_HPMCOUNTER30 = 74
let UC_RISCV_REG_HPMCOUNTER31 = 75
let UC_RISCV_REG_CYCLEH = 76
let UC_RISCV_REG_TIMEH = 77
let UC_RISCV_REG_INSTRETH = 78
let UC_RISCV_REG_HPMCOUNTER3H = 79
let UC_RISCV_REG_HPMCOUNTER4H = 80
let UC_RISCV_REG_HPMCOUNTER5H = 81
let UC_RISCV_REG_HPMCOUNTER6H = 82
let UC_RISCV_REG_HPMCOUNTER7H = 83
let UC_RISCV_REG_HPMCOUNTER8H = 84
let UC_RISCV_REG_HPMCOUNTER9H = 85
let UC_RISCV_REG_HPMCOUNTER10H = 86
let UC_RISCV_REG_HPMCOUNTER11H = 87
let UC_RISCV_REG_HPMCOUNTER12H = 88
let UC_RISCV_REG_HPMCOUNTER13H = 89
let UC_RISCV_REG_HPMCOUNTER14H = 90
let UC_RISCV_REG_HPMCOUNTER15H = 91
let UC_RISCV_REG_HPMCOUNTER16H = 92
let UC_RISCV_REG_HPMCOUNTER17H = 93
let UC_RISCV_REG_HPMCOUNTER18H = 94
let UC_RISCV_REG_HPMCOUNTER19H = 95
let UC_RISCV_REG_HPMCOUNTER20H = 96
let UC_RISCV_REG_HPMCOUNTER21H = 97
let UC_RISCV_REG_HPMCOUNTER22H = 98
let UC_RISCV_REG_HPMCOUNTER23H = 99
let UC_RISCV_REG_HPMCOUNTER24H = 100
let UC_RISCV_REG_HPMCOUNTER25H = 101
let UC_RISCV_REG_HPMCOUNTER26H = 102
let UC_RISCV_REG_HPMCOUNTER27H = 103
let UC_RISCV_REG_HPMCOUNTER28H = 104
let UC_RISCV_REG_HPMCOUNTER29H = 105
let UC_RISCV_REG_HPMCOUNTER30H = 106
let UC_RISCV_REG_HPMCOUNTER31H = 107
let UC_RISCV_REG_MCYCLE = 108
let UC_RISCV_REG_MINSTRET = 109
let UC_RISCV_REG_MCYCLEH = 110
let UC_RISCV_REG_MINSTRETH = 111
let UC_RISCV_REG_MVENDORID = 112
let UC_RISCV_REG_MARCHID = 113
let UC_RISCV_REG_MIMPID = 114
let UC_RISCV_REG_MHARTID = 115
let UC_RISCV_REG_MSTATUS = 116
let UC_RISCV_REG_MISA = 117
let UC_RISCV_REG_MEDELEG = 118
let UC_RISCV_REG_MIDELEG = 119
let UC_RISCV_REG_MIE = 120
let UC_RISCV_REG_MTVEC = 121
let UC_RISCV_REG_MCOUNTEREN = 122
let UC_RISCV_REG_MSTATUSH = 123
let UC_RISCV_REG_MUCOUNTEREN = 124
let UC_RISCV_REG_MSCOUNTEREN = 125
let UC_RISCV_REG_MHCOUNTEREN = 126
let UC_RISCV_REG_MSCRATCH = 127
let UC_RISCV_REG_MEPC = 128
let UC_RISCV_REG_MCAUSE = 129
let UC_RISCV_REG_MTVAL = 130
let UC_RISCV_REG_MIP = 131
let UC_RISCV_REG_MBADADDR = 132
let UC_RISCV_REG_SSTATUS = 133
let UC_RISCV_REG_SEDELEG = 134
let UC_RISCV_REG_SIDELEG = 135
let UC_RISCV_REG_SIE = 136
let UC_RISCV_REG_STVEC = 137
let UC_RISCV_REG_SCOUNTEREN = 138
let UC_RISCV_REG_SSCRATCH = 139
let UC_RISCV_REG_SEPC = 140
let UC_RISCV_REG_SCAUSE = 141
let UC_RISCV_REG_STVAL = 142
let UC_RISCV_REG_SIP = 143
let UC_RISCV_REG_SBADADDR = 144
let UC_RISCV_REG_SPTBR = 145
let UC_RISCV_REG_SATP = 146
let UC_RISCV_REG_HSTATUS = 147
let UC_RISCV_REG_HEDELEG = 148
let UC_RISCV_REG_HIDELEG = 149
let UC_RISCV_REG_HIE = 150
let UC_RISCV_REG_HCOUNTEREN = 151
let UC_RISCV_REG_HTVAL = 152
let UC_RISCV_REG_HIP = 153
let UC_RISCV_REG_HTINST = 154
let UC_RISCV_REG_HGATP = 155
let UC_RISCV_REG_HTIMEDELTA = 156
let UC_RISCV_REG_HTIMEDELTAH = 157
// Floating-point registers
let UC_RISCV_REG_F0 = 158
let UC_RISCV_REG_F1 = 159
let UC_RISCV_REG_F2 = 160
let UC_RISCV_REG_F3 = 161
let UC_RISCV_REG_F4 = 162
let UC_RISCV_REG_F5 = 163
let UC_RISCV_REG_F6 = 164
let UC_RISCV_REG_F7 = 165
let UC_RISCV_REG_F8 = 166
let UC_RISCV_REG_F9 = 167
let UC_RISCV_REG_F10 = 168
let UC_RISCV_REG_F11 = 169
let UC_RISCV_REG_F12 = 170
let UC_RISCV_REG_F13 = 171
let UC_RISCV_REG_F14 = 172
let UC_RISCV_REG_F15 = 173
let UC_RISCV_REG_F16 = 174
let UC_RISCV_REG_F17 = 175
let UC_RISCV_REG_F18 = 176
let UC_RISCV_REG_F19 = 177
let UC_RISCV_REG_F20 = 178
let UC_RISCV_REG_F21 = 179
let UC_RISCV_REG_F22 = 180
let UC_RISCV_REG_F23 = 181
let UC_RISCV_REG_F24 = 182
let UC_RISCV_REG_F25 = 183
let UC_RISCV_REG_F26 = 184
let UC_RISCV_REG_F27 = 185
let UC_RISCV_REG_F28 = 186
let UC_RISCV_REG_F29 = 187
let UC_RISCV_REG_F30 = 188
let UC_RISCV_REG_F31 = 189
let UC_RISCV_REG_PC = 190
let UC_RISCV_REG_ENDING = 191
// Alias registers
let UC_RISCV_REG_ZERO = 1
let UC_RISCV_REG_RA = 2
let UC_RISCV_REG_SP = 3
let UC_RISCV_REG_GP = 4
let UC_RISCV_REG_TP = 5
let UC_RISCV_REG_T0 = 6
let UC_RISCV_REG_T1 = 7
let UC_RISCV_REG_T2 = 8
let UC_RISCV_REG_S0 = 9
let UC_RISCV_REG_FP = 9
let UC_RISCV_REG_S1 = 10
let UC_RISCV_REG_A0 = 11
let UC_RISCV_REG_A1 = 12
let UC_RISCV_REG_A2 = 13
let UC_RISCV_REG_A3 = 14
let UC_RISCV_REG_A4 = 15
let UC_RISCV_REG_A5 = 16
let UC_RISCV_REG_A6 = 17
let UC_RISCV_REG_A7 = 18
let UC_RISCV_REG_S2 = 19
let UC_RISCV_REG_S3 = 20
let UC_RISCV_REG_S4 = 21
let UC_RISCV_REG_S5 = 22
let UC_RISCV_REG_S6 = 23
let UC_RISCV_REG_S7 = 24
let UC_RISCV_REG_S8 = 25
let UC_RISCV_REG_S9 = 26
let UC_RISCV_REG_S10 = 27
let UC_RISCV_REG_S11 = 28
let UC_RISCV_REG_T3 = 29
let UC_RISCV_REG_T4 = 30
let UC_RISCV_REG_T5 = 31
let UC_RISCV_REG_T6 = 32
let UC_RISCV_REG_FT0 = 158
let UC_RISCV_REG_FT1 = 159
let UC_RISCV_REG_FT2 = 160
let UC_RISCV_REG_FT3 = 161
let UC_RISCV_REG_FT4 = 162
let UC_RISCV_REG_FT5 = 163
let UC_RISCV_REG_FT6 = 164
let UC_RISCV_REG_FT7 = 165
let UC_RISCV_REG_FS0 = 166
let UC_RISCV_REG_FS1 = 167
let UC_RISCV_REG_FA0 = 168
let UC_RISCV_REG_FA1 = 169
let UC_RISCV_REG_FA2 = 170
let UC_RISCV_REG_FA3 = 171
let UC_RISCV_REG_FA4 = 172
let UC_RISCV_REG_FA5 = 173
let UC_RISCV_REG_FA6 = 174
let UC_RISCV_REG_FA7 = 175
let UC_RISCV_REG_FS2 = 176
let UC_RISCV_REG_FS3 = 177
let UC_RISCV_REG_FS4 = 178
let UC_RISCV_REG_FS5 = 179
let UC_RISCV_REG_FS6 = 180
let UC_RISCV_REG_FS7 = 181
let UC_RISCV_REG_FS8 = 182
let UC_RISCV_REG_FS9 = 183
let UC_RISCV_REG_FS10 = 184
let UC_RISCV_REG_FS11 = 185
let UC_RISCV_REG_FT8 = 186
let UC_RISCV_REG_FT9 = 187
let UC_RISCV_REG_FT10 = 188
let UC_RISCV_REG_FT11 = 189

130
bindings/dotnet/UnicornEngine/Const/S390x.fs Normal file
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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
namespace UnicornEngine.Const
open System
[<AutoOpen>]
module S390x =
// S390X CPU
let UC_CPU_S390X_Z900 = 0
let UC_CPU_S390X_Z900_2 = 1
let UC_CPU_S390X_Z900_3 = 2
let UC_CPU_S390X_Z800 = 3
let UC_CPU_S390X_Z990 = 4
let UC_CPU_S390X_Z990_2 = 5
let UC_CPU_S390X_Z990_3 = 6
let UC_CPU_S390X_Z890 = 7
let UC_CPU_S390X_Z990_4 = 8
let UC_CPU_S390X_Z890_2 = 9
let UC_CPU_S390X_Z990_5 = 10
let UC_CPU_S390X_Z890_3 = 11
let UC_CPU_S390X_Z9EC = 12
let UC_CPU_S390X_Z9EC_2 = 13
let UC_CPU_S390X_Z9BC = 14
let UC_CPU_S390X_Z9EC_3 = 15
let UC_CPU_S390X_Z9BC_2 = 16
let UC_CPU_S390X_Z10EC = 17
let UC_CPU_S390X_Z10EC_2 = 18
let UC_CPU_S390X_Z10BC = 19
let UC_CPU_S390X_Z10EC_3 = 20
let UC_CPU_S390X_Z10BC_2 = 21
let UC_CPU_S390X_Z196 = 22
let UC_CPU_S390X_Z196_2 = 23
let UC_CPU_S390X_Z114 = 24
let UC_CPU_S390X_ZEC12 = 25
let UC_CPU_S390X_ZEC12_2 = 26
let UC_CPU_S390X_ZBC12 = 27
let UC_CPU_S390X_Z13 = 28
let UC_CPU_S390X_Z13_2 = 29
let UC_CPU_S390X_Z13S = 30
let UC_CPU_S390X_Z14 = 31
let UC_CPU_S390X_Z14_2 = 32
let UC_CPU_S390X_Z14ZR1 = 33
let UC_CPU_S390X_GEN15A = 34
let UC_CPU_S390X_GEN15B = 35
let UC_CPU_S390X_QEMU = 36
let UC_CPU_S390X_MAX = 37
let UC_CPU_S390X_ENDING = 38
// S390X registers
let UC_S390X_REG_INVALID = 0
// General purpose registers
let UC_S390X_REG_R0 = 1
let UC_S390X_REG_R1 = 2
let UC_S390X_REG_R2 = 3
let UC_S390X_REG_R3 = 4
let UC_S390X_REG_R4 = 5
let UC_S390X_REG_R5 = 6
let UC_S390X_REG_R6 = 7
let UC_S390X_REG_R7 = 8
let UC_S390X_REG_R8 = 9
let UC_S390X_REG_R9 = 10
let UC_S390X_REG_R10 = 11
let UC_S390X_REG_R11 = 12
let UC_S390X_REG_R12 = 13
let UC_S390X_REG_R13 = 14
let UC_S390X_REG_R14 = 15
let UC_S390X_REG_R15 = 16
// Floating point registers
let UC_S390X_REG_F0 = 17
let UC_S390X_REG_F1 = 18
let UC_S390X_REG_F2 = 19
let UC_S390X_REG_F3 = 20
let UC_S390X_REG_F4 = 21
let UC_S390X_REG_F5 = 22
let UC_S390X_REG_F6 = 23
let UC_S390X_REG_F7 = 24
let UC_S390X_REG_F8 = 25
let UC_S390X_REG_F9 = 26
let UC_S390X_REG_F10 = 27
let UC_S390X_REG_F11 = 28
let UC_S390X_REG_F12 = 29
let UC_S390X_REG_F13 = 30
let UC_S390X_REG_F14 = 31
let UC_S390X_REG_F15 = 32
let UC_S390X_REG_F16 = 33
let UC_S390X_REG_F17 = 34
let UC_S390X_REG_F18 = 35
let UC_S390X_REG_F19 = 36
let UC_S390X_REG_F20 = 37
let UC_S390X_REG_F21 = 38
let UC_S390X_REG_F22 = 39
let UC_S390X_REG_F23 = 40
let UC_S390X_REG_F24 = 41
let UC_S390X_REG_F25 = 42
let UC_S390X_REG_F26 = 43
let UC_S390X_REG_F27 = 44
let UC_S390X_REG_F28 = 45
let UC_S390X_REG_F29 = 46
let UC_S390X_REG_F30 = 47
let UC_S390X_REG_F31 = 48
// Access registers
let UC_S390X_REG_A0 = 49
let UC_S390X_REG_A1 = 50
let UC_S390X_REG_A2 = 51
let UC_S390X_REG_A3 = 52
let UC_S390X_REG_A4 = 53
let UC_S390X_REG_A5 = 54
let UC_S390X_REG_A6 = 55
let UC_S390X_REG_A7 = 56
let UC_S390X_REG_A8 = 57
let UC_S390X_REG_A9 = 58
let UC_S390X_REG_A10 = 59
let UC_S390X_REG_A11 = 60
let UC_S390X_REG_A12 = 61
let UC_S390X_REG_A13 = 62
let UC_S390X_REG_A14 = 63
let UC_S390X_REG_A15 = 64
let UC_S390X_REG_PC = 65
let UC_S390X_REG_PSWM = 66
let UC_S390X_REG_ENDING = 67
// Alias registers

142
bindings/dotnet/UnicornEngine/Const/Sparc.fs Normal file
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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
namespace UnicornEngine.Const
open System
[<AutoOpen>]
module Sparc =
// SPARC32 CPU
let UC_CPU_SPARC32_FUJITSU_MB86904 = 0
let UC_CPU_SPARC32_FUJITSU_MB86907 = 1
let UC_CPU_SPARC32_TI_MICROSPARC_I = 2
let UC_CPU_SPARC32_TI_MICROSPARC_II = 3
let UC_CPU_SPARC32_TI_MICROSPARC_IIEP = 4
let UC_CPU_SPARC32_TI_SUPERSPARC_40 = 5
let UC_CPU_SPARC32_TI_SUPERSPARC_50 = 6
let UC_CPU_SPARC32_TI_SUPERSPARC_51 = 7
let UC_CPU_SPARC32_TI_SUPERSPARC_60 = 8
let UC_CPU_SPARC32_TI_SUPERSPARC_61 = 9
let UC_CPU_SPARC32_TI_SUPERSPARC_II = 10
let UC_CPU_SPARC32_LEON2 = 11
let UC_CPU_SPARC32_LEON3 = 12
let UC_CPU_SPARC32_ENDING = 13
// SPARC64 CPU
let UC_CPU_SPARC64_FUJITSU = 0
let UC_CPU_SPARC64_FUJITSU_III = 1
let UC_CPU_SPARC64_FUJITSU_IV = 2
let UC_CPU_SPARC64_FUJITSU_V = 3
let UC_CPU_SPARC64_TI_ULTRASPARC_I = 4
let UC_CPU_SPARC64_TI_ULTRASPARC_II = 5
let UC_CPU_SPARC64_TI_ULTRASPARC_III = 6
let UC_CPU_SPARC64_TI_ULTRASPARC_IIE = 7
let UC_CPU_SPARC64_SUN_ULTRASPARC_III = 8
let UC_CPU_SPARC64_SUN_ULTRASPARC_III_CU = 9
let UC_CPU_SPARC64_SUN_ULTRASPARC_IIII = 10
let UC_CPU_SPARC64_SUN_ULTRASPARC_IV = 11
let UC_CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS = 12
let UC_CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS = 13
let UC_CPU_SPARC64_SUN_ULTRASPARC_T1 = 14
let UC_CPU_SPARC64_SUN_ULTRASPARC_T2 = 15
let UC_CPU_SPARC64_NEC_ULTRASPARC_I = 16
let UC_CPU_SPARC64_ENDING = 17
// SPARC registers
let UC_SPARC_REG_INVALID = 0
let UC_SPARC_REG_F0 = 1
let UC_SPARC_REG_F1 = 2
let UC_SPARC_REG_F2 = 3
let UC_SPARC_REG_F3 = 4
let UC_SPARC_REG_F4 = 5
let UC_SPARC_REG_F5 = 6
let UC_SPARC_REG_F6 = 7
let UC_SPARC_REG_F7 = 8
let UC_SPARC_REG_F8 = 9
let UC_SPARC_REG_F9 = 10
let UC_SPARC_REG_F10 = 11
let UC_SPARC_REG_F11 = 12
let UC_SPARC_REG_F12 = 13
let UC_SPARC_REG_F13 = 14
let UC_SPARC_REG_F14 = 15
let UC_SPARC_REG_F15 = 16
let UC_SPARC_REG_F16 = 17
let UC_SPARC_REG_F17 = 18
let UC_SPARC_REG_F18 = 19
let UC_SPARC_REG_F19 = 20
let UC_SPARC_REG_F20 = 21
let UC_SPARC_REG_F21 = 22
let UC_SPARC_REG_F22 = 23
let UC_SPARC_REG_F23 = 24
let UC_SPARC_REG_F24 = 25
let UC_SPARC_REG_F25 = 26
let UC_SPARC_REG_F26 = 27
let UC_SPARC_REG_F27 = 28
let UC_SPARC_REG_F28 = 29
let UC_SPARC_REG_F29 = 30
let UC_SPARC_REG_F30 = 31
let UC_SPARC_REG_F31 = 32
let UC_SPARC_REG_F32 = 33
let UC_SPARC_REG_F34 = 34
let UC_SPARC_REG_F36 = 35
let UC_SPARC_REG_F38 = 36
let UC_SPARC_REG_F40 = 37
let UC_SPARC_REG_F42 = 38
let UC_SPARC_REG_F44 = 39
let UC_SPARC_REG_F46 = 40
let UC_SPARC_REG_F48 = 41
let UC_SPARC_REG_F50 = 42
let UC_SPARC_REG_F52 = 43
let UC_SPARC_REG_F54 = 44
let UC_SPARC_REG_F56 = 45
let UC_SPARC_REG_F58 = 46
let UC_SPARC_REG_F60 = 47
let UC_SPARC_REG_F62 = 48
let UC_SPARC_REG_FCC0 = 49
let UC_SPARC_REG_FCC1 = 50
let UC_SPARC_REG_FCC2 = 51
let UC_SPARC_REG_FCC3 = 52
let UC_SPARC_REG_G0 = 53
let UC_SPARC_REG_G1 = 54
let UC_SPARC_REG_G2 = 55
let UC_SPARC_REG_G3 = 56
let UC_SPARC_REG_G4 = 57
let UC_SPARC_REG_G5 = 58
let UC_SPARC_REG_G6 = 59
let UC_SPARC_REG_G7 = 60
let UC_SPARC_REG_I0 = 61
let UC_SPARC_REG_I1 = 62
let UC_SPARC_REG_I2 = 63
let UC_SPARC_REG_I3 = 64
let UC_SPARC_REG_I4 = 65
let UC_SPARC_REG_I5 = 66
let UC_SPARC_REG_FP = 67
let UC_SPARC_REG_I7 = 68
let UC_SPARC_REG_ICC = 69
let UC_SPARC_REG_L0 = 70
let UC_SPARC_REG_L1 = 71
let UC_SPARC_REG_L2 = 72
let UC_SPARC_REG_L3 = 73
let UC_SPARC_REG_L4 = 74
let UC_SPARC_REG_L5 = 75
let UC_SPARC_REG_L6 = 76
let UC_SPARC_REG_L7 = 77
let UC_SPARC_REG_O0 = 78
let UC_SPARC_REG_O1 = 79
let UC_SPARC_REG_O2 = 80
let UC_SPARC_REG_O3 = 81
let UC_SPARC_REG_O4 = 82
let UC_SPARC_REG_O5 = 83
let UC_SPARC_REG_SP = 84
let UC_SPARC_REG_O7 = 85
let UC_SPARC_REG_Y = 86
let UC_SPARC_REG_XCC = 87
let UC_SPARC_REG_PC = 88
let UC_SPARC_REG_ENDING = 89
let UC_SPARC_REG_O6 = 84
let UC_SPARC_REG_I6 = 67

132
bindings/dotnet/UnicornEngine/Const/TriCore.fs Normal file
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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
namespace UnicornEngine.Const
open System
[<AutoOpen>]
module TriCore =
// TRICORE CPU
let UC_CPU_TRICORE_TC1796 = 0
let UC_CPU_TRICORE_TC1797 = 1
let UC_CPU_TRICORE_TC27X = 2
let UC_CPU_TRICORE_ENDING = 3
// TRICORE registers
let UC_TRICORE_REG_INVALID = 0
let UC_TRICORE_REG_A0 = 1
let UC_TRICORE_REG_A1 = 2
let UC_TRICORE_REG_A2 = 3
let UC_TRICORE_REG_A3 = 4
let UC_TRICORE_REG_A4 = 5
let UC_TRICORE_REG_A5 = 6
let UC_TRICORE_REG_A6 = 7
let UC_TRICORE_REG_A7 = 8
let UC_TRICORE_REG_A8 = 9
let UC_TRICORE_REG_A9 = 10
let UC_TRICORE_REG_A10 = 11
let UC_TRICORE_REG_A11 = 12
let UC_TRICORE_REG_A12 = 13
let UC_TRICORE_REG_A13 = 14
let UC_TRICORE_REG_A14 = 15
let UC_TRICORE_REG_A15 = 16
let UC_TRICORE_REG_D0 = 17
let UC_TRICORE_REG_D1 = 18
let UC_TRICORE_REG_D2 = 19
let UC_TRICORE_REG_D3 = 20
let UC_TRICORE_REG_D4 = 21
let UC_TRICORE_REG_D5 = 22
let UC_TRICORE_REG_D6 = 23
let UC_TRICORE_REG_D7 = 24
let UC_TRICORE_REG_D8 = 25
let UC_TRICORE_REG_D9 = 26
let UC_TRICORE_REG_D10 = 27
let UC_TRICORE_REG_D11 = 28
let UC_TRICORE_REG_D12 = 29
let UC_TRICORE_REG_D13 = 30
let UC_TRICORE_REG_D14 = 31
let UC_TRICORE_REG_D15 = 32
let UC_TRICORE_REG_PCXI = 33
let UC_TRICORE_REG_PSW = 34
let UC_TRICORE_REG_PSW_USB_C = 35
let UC_TRICORE_REG_PSW_USB_V = 36
let UC_TRICORE_REG_PSW_USB_SV = 37
let UC_TRICORE_REG_PSW_USB_AV = 38
let UC_TRICORE_REG_PSW_USB_SAV = 39
let UC_TRICORE_REG_PC = 40
let UC_TRICORE_REG_SYSCON = 41
let UC_TRICORE_REG_CPU_ID = 42
let UC_TRICORE_REG_BIV = 43
let UC_TRICORE_REG_BTV = 44
let UC_TRICORE_REG_ISP = 45
let UC_TRICORE_REG_ICR = 46
let UC_TRICORE_REG_FCX = 47
let UC_TRICORE_REG_LCX = 48
let UC_TRICORE_REG_COMPAT = 49
let UC_TRICORE_REG_DPR0_U = 50
let UC_TRICORE_REG_DPR1_U = 51
let UC_TRICORE_REG_DPR2_U = 52
let UC_TRICORE_REG_DPR3_U = 53
let UC_TRICORE_REG_DPR0_L = 54
let UC_TRICORE_REG_DPR1_L = 55
let UC_TRICORE_REG_DPR2_L = 56
let UC_TRICORE_REG_DPR3_L = 57
let UC_TRICORE_REG_CPR0_U = 58
let UC_TRICORE_REG_CPR1_U = 59
let UC_TRICORE_REG_CPR2_U = 60
let UC_TRICORE_REG_CPR3_U = 61
let UC_TRICORE_REG_CPR0_L = 62
let UC_TRICORE_REG_CPR1_L = 63
let UC_TRICORE_REG_CPR2_L = 64
let UC_TRICORE_REG_CPR3_L = 65
let UC_TRICORE_REG_DPM0 = 66
let UC_TRICORE_REG_DPM1 = 67
let UC_TRICORE_REG_DPM2 = 68
let UC_TRICORE_REG_DPM3 = 69
let UC_TRICORE_REG_CPM0 = 70
let UC_TRICORE_REG_CPM1 = 71
let UC_TRICORE_REG_CPM2 = 72
let UC_TRICORE_REG_CPM3 = 73
let UC_TRICORE_REG_MMU_CON = 74
let UC_TRICORE_REG_MMU_ASI = 75
let UC_TRICORE_REG_MMU_TVA = 76
let UC_TRICORE_REG_MMU_TPA = 77
let UC_TRICORE_REG_MMU_TPX = 78
let UC_TRICORE_REG_MMU_TFA = 79
let UC_TRICORE_REG_BMACON = 80
let UC_TRICORE_REG_SMACON = 81
let UC_TRICORE_REG_DIEAR = 82
let UC_TRICORE_REG_DIETR = 83
let UC_TRICORE_REG_CCDIER = 84
let UC_TRICORE_REG_MIECON = 85
let UC_TRICORE_REG_PIEAR = 86
let UC_TRICORE_REG_PIETR = 87
let UC_TRICORE_REG_CCPIER = 88
let UC_TRICORE_REG_DBGSR = 89
let UC_TRICORE_REG_EXEVT = 90
let UC_TRICORE_REG_CREVT = 91
let UC_TRICORE_REG_SWEVT = 92
let UC_TRICORE_REG_TR0EVT = 93
let UC_TRICORE_REG_TR1EVT = 94
let UC_TRICORE_REG_DMS = 95
let UC_TRICORE_REG_DCX = 96
let UC_TRICORE_REG_DBGTCR = 97
let UC_TRICORE_REG_CCTRL = 98
let UC_TRICORE_REG_CCNT = 99
let UC_TRICORE_REG_ICNT = 100
let UC_TRICORE_REG_M1CNT = 101
let UC_TRICORE_REG_M2CNT = 102
let UC_TRICORE_REG_M3CNT = 103
let UC_TRICORE_REG_ENDING = 104
let UC_TRICORE_REG_GA0 = 1
let UC_TRICORE_REG_GA1 = 2
let UC_TRICORE_REG_GA8 = 9
let UC_TRICORE_REG_GA9 = 10
let UC_TRICORE_REG_SP = 11
let UC_TRICORE_REG_LR = 12
let UC_TRICORE_REG_IA = 16
let UC_TRICORE_REG_ID = 32

1636
bindings/dotnet/UnicornEngine/Const/X86.fs Normal file
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