lazymio/unicorn
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

This code should now build the x86_x64-softmmu part 2.

Browse Source
This commit is contained in:
xorstream
2017-01-19 22:50:28 +11:00
parent 37f9a248ea
commit 1aeaf5c40d
174 changed files with 2418 additions and 1414 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
qemu/target-i386/cc_helper.c
View File

@@ -218,7 +218,7 @@ target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1,
uint32_t cpu_cc_compute_all(CPUX86State *env, int op)
{
return helper_cc_compute_all(CC_DST, CC_SRC, CC_SRC2, op);
return (uint32_t)helper_cc_compute_all(CC_DST, CC_SRC, CC_SRC2, op);
}
target_ulong helper_cc_compute_c(target_ulong dst, target_ulong src1,
@@ -323,7 +323,7 @@ target_ulong helper_cc_compute_c(target_ulong dst, target_ulong src1,
void helper_write_eflags(CPUX86State *env, target_ulong t0,
uint32_t update_mask)
{
cpu_load_eflags(env, t0, update_mask);
cpu_load_eflags(env, (int)t0, update_mask);
}
target_ulong helper_read_eflags(CPUX86State *env)

4
qemu/target-i386/cc_helper_template.h
View File

@@ -141,7 +141,7 @@ static int glue(compute_all_inc, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1)
int cf, pf, af, zf, sf, of;
DATA_TYPE src2;
cf = src1;
cf = (int)src1;
src1 = dst - 1;
src2 = 1;
pf = parity_table[(uint8_t)dst];
@@ -157,7 +157,7 @@ static int glue(compute_all_dec, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1)
int cf, pf, af, zf, sf, of;
DATA_TYPE src2;
cf = src1;
cf = (int)src1;
src1 = dst + 1;
src2 = 1;
pf = parity_table[(uint8_t)dst];

735
qemu/target-i386/cpu.c
View File

File diff suppressed because it is too large Load Diff

8
qemu/target-i386/cpu.h
View File

@@ -805,7 +805,7 @@ typedef struct BNDCSReg {
#define MMX_Q(n) q
typedef union {
floatx80 d __attribute__((aligned(16)));
floatx80 QEMU_ALIGN(16, d);
MMXReg mmx;
} FPReg;
@@ -869,7 +869,8 @@ typedef struct CPUX86State {
uint64_t msr_bndcfgs;
/* Beginning of state preserved by INIT (dummy marker). */
struct {} start_init_save;
//struct {} start_init_save;
int start_init_save;
/* FPU state */
unsigned int fpstt; /* top of stack index */
@@ -937,7 +938,8 @@ typedef struct CPUX86State {
uint32_t smbase;
/* End of state preserved by INIT (dummy marker). */
struct {} end_init_save;
//struct {} end_init_save;
int end_init_save;
uint64_t system_time_msr;
uint64_t wall_clock_msr;

52
qemu/target-i386/fpu_helper.c
View File

@@ -489,42 +489,58 @@ void helper_fabs_ST0(CPUX86State *env)
void helper_fld1_ST0(CPUX86State *env)
{
ST0 = floatx80_one;
//ST0 = floatx80_one;
floatx80 one = { 0x8000000000000000LL, 0x3fff };
ST0 = one;
}
void helper_fldl2t_ST0(CPUX86State *env)
{
ST0 = floatx80_l2t;
//ST0 = floatx80_l2t;
floatx80 l2t = { 0xd49a784bcd1b8afeLL, 0x4000 };
ST0 = l2t;
}
void helper_fldl2e_ST0(CPUX86State *env)
{
ST0 = floatx80_l2e;
//ST0 = floatx80_l2e;
floatx80 l2e = { 0xb8aa3b295c17f0bcLL, 0x3fff };
ST0 = l2e;
}
void helper_fldpi_ST0(CPUX86State *env)
{
ST0 = floatx80_pi;
//ST0 = floatx80_pi;
floatx80 pi = { 0xc90fdaa22168c235LL, 0x4000 };
ST0 = pi;
}
void helper_fldlg2_ST0(CPUX86State *env)
{
ST0 = floatx80_lg2;
//ST0 = floatx80_lg2;
floatx80 lg2 = { 0x9a209a84fbcff799LL, 0x3ffd };
ST0 = lg2;
}
void helper_fldln2_ST0(CPUX86State *env)
{
ST0 = floatx80_ln2;
//ST0 = floatx80_ln2;
floatx80 ln2 = { 0xb17217f7d1cf79acLL, 0x3ffe };
ST0 = ln2;
}
void helper_fldz_ST0(CPUX86State *env)
{
ST0 = floatx80_zero;
//ST0 = floatx80_zero;
floatx80 zero = { 0x0000000000000000LL, 0x0000 };
ST0 = zero;
}
void helper_fldz_FT0(CPUX86State *env)
{
FT0 = floatx80_zero;
//FT0 = floatx80_zero;
floatx80 zero = { 0x0000000000000000LL, 0x0000 };
ST0 = zero;
}
uint32_t helper_fnstsw(CPUX86State *env)
@@ -686,10 +702,11 @@ void helper_fptan(CPUX86State *env)
if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
env->fpus |= 0x400;
} else {
fptemp = tan(fptemp);
floatx80 one = { 0x8000000000000000LL, 0x3fff };
fptemp = tan(fptemp);
ST0 = double_to_floatx80(env, fptemp);
fpush(env);
ST0 = floatx80_one;
ST0 = one;
env->fpus &= ~0x400; /* C2 <-- 0 */
/* the above code is for |arg| < 2**52 only */
}
@@ -713,7 +730,9 @@ void helper_fxtract(CPUX86State *env)
if (floatx80_is_zero(ST0)) {
/* Easy way to generate -inf and raising division by 0 exception */
ST0 = floatx80_div(floatx80_chs(floatx80_one), floatx80_zero,
floatx80 zero = { 0x0000000000000000LL, 0x0000 };
floatx80 one = { 0x8000000000000000LL, 0x3fff };
ST0 = floatx80_div(floatx80_chs(one), zero,
&env->fp_status);
fpush(env);
ST0 = temp.d;
@@ -740,7 +759,8 @@ void helper_fprem1(CPUX86State *env)
st1 = floatx80_to_double(env, ST1);
if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) {
ST0 = double_to_floatx80(env, 0.0 / 0.0); /* NaN */
ST0 = double_to_floatx80(env, NAN); /* NaN */
env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
return;
}
@@ -799,7 +819,7 @@ void helper_fprem(CPUX86State *env)
st1 = floatx80_to_double(env, ST1);
if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) {
ST0 = double_to_floatx80(env, 0.0 / 0.0); /* NaN */
ST0 = double_to_floatx80(env, NAN); /* NaN */
env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
return;
}
@@ -992,7 +1012,7 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32)
cpu_stl_data(env, ptr, env->fpuc);
cpu_stl_data(env, ptr + 4, fpus);
cpu_stl_data(env, ptr + 8, fptag);
cpu_stl_data(env, ptr + 12, env->fpip); /* fpip */
cpu_stl_data(env, ptr + 12, (uint32_t)env->fpip); /* fpip */
cpu_stl_data(env, ptr + 20, 0); /* fpcs */
cpu_stl_data(env, ptr + 24, 0); /* fpoo */
cpu_stl_data(env, ptr + 28, 0); /* fpos */
@@ -1001,7 +1021,7 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32)
cpu_stl_data(env, ptr, env->fpuc);
cpu_stl_data(env, ptr + 4, fpus);
cpu_stl_data(env, ptr + 8, fptag);
cpu_stl_data(env, ptr + 12, env->fpip); /* fpip */
cpu_stl_data(env, ptr + 12, (uint32_t)env->fpip); /* fpip */
cpu_stl_data(env, ptr + 16, 0); /* fpcs */
cpu_stl_data(env, ptr + 20, 0); /* fpoo */
cpu_stl_data(env, ptr + 24, 0); /* fpos */
@@ -1010,7 +1030,7 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32)
cpu_stw_data(env, ptr, env->fpuc);
cpu_stw_data(env, ptr + 2, fpus);
cpu_stw_data(env, ptr + 4, fptag);
cpu_stw_data(env, ptr + 6, env->fpip);
cpu_stw_data(env, ptr + 6, (uint32_t)env->fpip);
cpu_stw_data(env, ptr + 8, 0);
cpu_stw_data(env, ptr + 10, 0);
cpu_stw_data(env, ptr + 12, 0);

4
qemu/target-i386/helper.c
View File

@@ -1002,7 +1002,7 @@ bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update)
break;
}
if (bp_match || wp_match) {
dr6 |= 1 << reg;
dr6 |= 1ULL << reg;
if (hw_breakpoint_enabled(env->dr[7], reg)) {
hit_enabled = true;
}
@@ -1083,7 +1083,7 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
dt = &env->gdt;
index = selector & ~7;
ptr = dt->base + index;
if ((index + 7) > dt->limit
if ((uint32_t)(index + 7) > dt->limit
|| cpu_memory_rw_debug(cs, ptr, (uint8_t *)&e1, sizeof(e1), 0) != 0
|| cpu_memory_rw_debug(cs, ptr+4, (uint8_t *)&e2, sizeof(e2), 0) != 0)
return 0;

8
qemu/target-i386/int_helper.c
View File

@@ -121,7 +121,7 @@ void helper_divl_EAX(CPUX86State *env, target_ulong t0)
uint64_t num, q;
num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
den = t0;
den = (unsigned int)t0;
if (den == 0) {
raise_exception(env, EXCP00_DIVZ);
}
@@ -140,7 +140,7 @@ void helper_idivl_EAX(CPUX86State *env, target_ulong t0)
int64_t num, q;
num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
den = t0;
den = (int)t0;
if (den == 0) {
raise_exception(env, EXCP00_DIVZ);
}
@@ -362,14 +362,14 @@ static int idiv64(uint64_t *plow, uint64_t *phigh, int64_t b)
if (*plow > (1ULL << 63)) {
return 1;
}
*plow = -*plow;
*plow = 0-*plow;
} else {
if (*plow >= (1ULL << 63)) {
return 1;
}
}
if (sa) {
*phigh = -*phigh;
*phigh = 0-*phigh;
}
return 0;
}

6
qemu/target-i386/misc_helper.c
View File

@@ -126,17 +126,17 @@ void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0);
switch (reg) {
case 0:
cpu_x86_update_cr0(env, t0);
cpu_x86_update_cr0(env, (uint32_t)t0);
break;
case 3:
cpu_x86_update_cr3(env, t0);
break;
case 4:
cpu_x86_update_cr4(env, t0);
cpu_x86_update_cr4(env, (uint32_t)t0);
break;
case 8:
if (!(env->hflags2 & HF2_VINTR_MASK)) {
cpu_set_apic_tpr(env->uc, x86_env_get_cpu(env)->apic_state, t0);
cpu_set_apic_tpr(env->uc, x86_env_get_cpu(env)->apic_state, (uint8_t)t0);
}
env->v_tpr = t0 & 0x0f;
break;

2
qemu/target-i386/ops_sse.h
View File

@@ -1945,7 +1945,7 @@ static inline int pcmp_elen(CPUX86State *env, int reg, uint32_t ctrl)
/* Presence of REX.W is indicated by a bit higher than 7 set */
if (ctrl >> 8) {
val = abs1((int64_t)env->regs[reg]);
val = abs1((int)env->regs[reg]);
} else {
val = abs1((int32_t)env->regs[reg]);
}

5
qemu/target-i386/seg_helper.c
View File

@@ -947,6 +947,7 @@ void helper_syscall(CPUX86State *env, int next_eip_addend)
{
// Unicorn: call registered syscall hooks
struct hook *hook;
HOOK_FOREACH_VAR_DECLARE;
HOOK_FOREACH(env->uc, hook, UC_HOOK_INSN) {
if (!HOOK_BOUND_CHECK(hook, env->eip))
continue;
@@ -956,7 +957,7 @@ void helper_syscall(CPUX86State *env, int next_eip_addend)
env->eip += next_eip_addend;
return;
/*
int selector;
if (!(env->efer & MSR_EFER_SCE)) {
@@ -1005,6 +1006,7 @@ void helper_syscall(CPUX86State *env, int next_eip_addend)
DESC_W_MASK | DESC_A_MASK);
env->eip = (uint32_t)env->star;
}
*/
}
#endif
#endif
@@ -2307,6 +2309,7 @@ void helper_sysenter(CPUX86State *env, int next_eip_addend)
{
// Unicorn: call registered SYSENTER hooks
struct hook *hook;
HOOK_FOREACH_VAR_DECLARE;
HOOK_FOREACH(env->uc, hook, UC_HOOK_INSN) {
if (!HOOK_BOUND_CHECK(hook, env->eip))
continue;

4
qemu/target-i386/shift_helper_template.h
View File

@@ -55,7 +55,7 @@ target_ulong glue(helper_rcl, SUFFIX)(CPUX86State *env, target_ulong t0,
count = rclb_table[count];
#endif
if (count) {
eflags = env->cc_src;
eflags = (int)env->cc_src;
t0 &= DATA_MASK;
src = t0;
res = (t0 << count) | ((target_ulong)(eflags & CC_C) << (count - 1));
@@ -84,7 +84,7 @@ target_ulong glue(helper_rcr, SUFFIX)(CPUX86State *env, target_ulong t0,
count = rclb_table[count];
#endif
if (count) {
eflags = env->cc_src;
eflags = (int)env->cc_src;
t0 &= DATA_MASK;
src = t0;
res = (t0 >> count) |

10
qemu/target-i386/smm_helper.c
View File

@@ -97,12 +97,12 @@ void do_smm_enter(X86CPU *cpu)
}
stq_phys(cs->as, sm_state + 0x7f78, env->eip);
stl_phys(cs->as, sm_state + 0x7f70, cpu_compute_eflags(env));
stl_phys(cs->as, sm_state + 0x7f68, env->dr[6]);
stl_phys(cs->as, sm_state + 0x7f60, env->dr[7]);
stl_phys(cs->as, sm_state + 0x7f68, (uint32_t)env->dr[6]);
stl_phys(cs->as, sm_state + 0x7f60, (uint32_t)env->dr[7]);
stl_phys(cs->as, sm_state + 0x7f48, env->cr[4]);
stl_phys(cs->as, sm_state + 0x7f50, env->cr[3]);
stl_phys(cs->as, sm_state + 0x7f58, env->cr[0]);
stl_phys(cs->as, sm_state + 0x7f48, (uint32_t)env->cr[4]);
stl_phys(cs->as, sm_state + 0x7f50, (uint32_t)env->cr[3]);
stl_phys(cs->as, sm_state + 0x7f58, (uint32_t)env->cr[0]);
stl_phys(cs->as, sm_state + 0x7efc, SMM_REVISION_ID);
stl_phys(cs->as, sm_state + 0x7f00, env->smbase);

16
qemu/target-i386/svm.h
View File

@@ -130,7 +130,7 @@
#define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */
struct QEMU_PACKED vmcb_control_area {
QEMU_PACK( struct vmcb_control_area {
uint16_t intercept_cr_read;
uint16_t intercept_cr_write;
uint16_t intercept_dr_read;
@@ -160,16 +160,16 @@ struct QEMU_PACKED vmcb_control_area {
uint64_t nested_cr3;
uint64_t lbr_ctl;
uint8_t reserved_5[832];
};
});
struct QEMU_PACKED vmcb_seg {
QEMU_PACK( struct vmcb_seg {
uint16_t selector;
uint16_t attrib;
uint32_t limit;
uint64_t base;
};
});
struct QEMU_PACKED vmcb_save_area {
QEMU_PACK( struct vmcb_save_area {
struct vmcb_seg es;
struct vmcb_seg cs;
struct vmcb_seg ss;
@@ -212,11 +212,11 @@ struct QEMU_PACKED vmcb_save_area {
uint64_t br_to;
uint64_t last_excp_from;
uint64_t last_excp_to;
};
});
struct QEMU_PACKED vmcb {
QEMU_PACK( struct vmcb {
struct vmcb_control_area control;
struct vmcb_save_area save;
};
});
#endif

38
qemu/target-i386/svm_helper.c
View File

@@ -486,33 +486,27 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
if (likely(!(env->hflags & HF_SVMI_MASK))) {
return;
}
switch (type) {
case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR0 + 8:
if( type >= SVM_EXIT_READ_CR0 && type <= SVM_EXIT_READ_CR0 + 8 ) {
if (env->intercept_cr_read & (1 << (type - SVM_EXIT_READ_CR0))) {
helper_vmexit(env, type, param);
}
break;
case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR0 + 8:
} else if( type >= SVM_EXIT_WRITE_CR0 && type <= SVM_EXIT_WRITE_CR0 + 8 ) {
if (env->intercept_cr_write & (1 << (type - SVM_EXIT_WRITE_CR0))) {
helper_vmexit(env, type, param);
}
break;
case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR0 + 7:
} else if( type >= SVM_EXIT_READ_DR0 && type <= SVM_EXIT_READ_DR0 + 7 ) {
if (env->intercept_dr_read & (1 << (type - SVM_EXIT_READ_DR0))) {
helper_vmexit(env, type, param);
}
break;
case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR0 + 7:
} else if( type >= SVM_EXIT_WRITE_DR0 && type <= SVM_EXIT_WRITE_DR0 + 7 ) {
if (env->intercept_dr_write & (1 << (type - SVM_EXIT_WRITE_DR0))) {
helper_vmexit(env, type, param);
}
break;
case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 31:
} else if( type >= SVM_EXIT_EXCP_BASE && type <= SVM_EXIT_EXCP_BASE + 31 ) {
if (env->intercept_exceptions & (1 << (type - SVM_EXIT_EXCP_BASE))) {
helper_vmexit(env, type, param);
}
break;
case SVM_EXIT_MSR:
} else if( type == SVM_EXIT_MSR ) {
if (env->intercept & (1ULL << (SVM_EXIT_MSR - SVM_EXIT_INTR))) {
/* FIXME: this should be read in at vmrun (faster this way?) */
uint64_t addr = ldq_phys(cs->as, env->vm_vmcb +
@@ -520,38 +514,32 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
control.msrpm_base_pa));
uint32_t t0, t1;
switch ((uint32_t)env->regs[R_ECX]) {
case 0 ... 0x1fff:
uint32_t ecx = (uint32_t)env->regs[R_ECX];
if( ecx >= 0 && ecx <= 0x1fff ) {
t0 = (env->regs[R_ECX] * 2) % 8;
t1 = (env->regs[R_ECX] * 2) / 8;
break;
case 0xc0000000 ... 0xc0001fff:
} else if( ecx >= 0xc0000000 && ecx <= 0xc0001fff ) {
t0 = (8192 + env->regs[R_ECX] - 0xc0000000) * 2;
t1 = (t0 / 8);
t0 %= 8;
break;
case 0xc0010000 ... 0xc0011fff:
} else if( ecx >= 0xc0010000 && ecx <= 0xc0011fff ) {
t0 = (16384 + env->regs[R_ECX] - 0xc0010000) * 2;
t1 = (t0 / 8);
t0 %= 8;
break;
default:
} else {
helper_vmexit(env, type, param);
t0 = 0;
t1 = 0;
break;
}
if (ldub_phys(cs->as, addr + t1) & ((1 << param) << t0)) {
helper_vmexit(env, type, param);
}
}
break;
default:
} else {
if (env->intercept & (1ULL << (type - SVM_EXIT_INTR))) {
helper_vmexit(env, type, param);
}
break;
}
}
}
void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type,

2
qemu/target-i386/topology.h
View File

@@ -38,7 +38,7 @@
* CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width().
*/
#include <stdint.h>
#include "platform.h"
#include <string.h>
#include "qemu/bitops.h"

1080
qemu/target-i386/translate.c
View File

File diff suppressed because it is too large Load Diff

104
qemu/target-i386/unicorn.c
View File

@@ -150,10 +150,17 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
switch(regid) {
default:
break;
case UC_X86_REG_FP0 ... UC_X86_REG_FP7:
case UC_X86_REG_FP0:
case UC_X86_REG_FP1:
case UC_X86_REG_FP2:
case UC_X86_REG_FP3:
case UC_X86_REG_FP4:
case UC_X86_REG_FP5:
case UC_X86_REG_FP6:
case UC_X86_REG_FP7:
{
floatx80 reg = X86_CPU(uc, mycpu)->env.fpregs[regid - UC_X86_REG_FP0].d;
cpu_get_fp80(value, value+sizeof(uint64_t), reg);
cpu_get_fp80(value, (uint16_t*)((char*)value+sizeof(uint64_t)), reg);
}
continue;
case UC_X86_REG_FPSW:
@@ -197,7 +204,14 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
*(uint16_t*) value = fptag;
}
continue;
case UC_X86_REG_XMM0 ... UC_X86_REG_XMM7:
case UC_X86_REG_XMM0:
case UC_X86_REG_XMM1:
case UC_X86_REG_XMM2:
case UC_X86_REG_XMM3:
case UC_X86_REG_XMM4:
case UC_X86_REG_XMM5:
case UC_X86_REG_XMM6:
case UC_X86_REG_XMM7:
{
float64 *dst = (float64*)value;
XMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0];
@@ -234,10 +248,21 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
switch(regid) {
default:
break;
case UC_X86_REG_CR0 ... UC_X86_REG_CR4:
case UC_X86_REG_CR0:
case UC_X86_REG_CR1:
case UC_X86_REG_CR2:
case UC_X86_REG_CR3:
case UC_X86_REG_CR4:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0];
break;
case UC_X86_REG_DR0 ... UC_X86_REG_DR7:
case UC_X86_REG_DR0:
case UC_X86_REG_DR1:
case UC_X86_REG_DR2:
case UC_X86_REG_DR3:
case UC_X86_REG_DR4:
case UC_X86_REG_DR5:
case UC_X86_REG_DR6:
case UC_X86_REG_DR7:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0];
break;
case UC_X86_REG_EFLAGS:
@@ -367,10 +392,21 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
switch(regid) {
default:
break;
case UC_X86_REG_CR0 ... UC_X86_REG_CR4:
case UC_X86_REG_CR0:
case UC_X86_REG_CR1:
case UC_X86_REG_CR2:
case UC_X86_REG_CR3:
case UC_X86_REG_CR4:
*(int64_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0];
break;
case UC_X86_REG_DR0 ... UC_X86_REG_DR7:
case UC_X86_REG_DR0:
case UC_X86_REG_DR1:
case UC_X86_REG_DR2:
case UC_X86_REG_DR3:
case UC_X86_REG_DR4:
case UC_X86_REG_DR5:
case UC_X86_REG_DR6:
case UC_X86_REG_DR7:
*(int64_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0];
break;
case UC_X86_REG_EFLAGS:
@@ -647,10 +683,17 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
switch(regid) {
default:
break;
case UC_X86_REG_FP0 ... UC_X86_REG_FP7:
case UC_X86_REG_FP0:
case UC_X86_REG_FP1:
case UC_X86_REG_FP2:
case UC_X86_REG_FP3:
case UC_X86_REG_FP4:
case UC_X86_REG_FP5:
case UC_X86_REG_FP6:
case UC_X86_REG_FP7:
{
uint64_t mant = *(uint64_t*) value;
uint16_t upper = *(uint16_t*) (value + sizeof(uint64_t));
uint16_t upper = *(uint16_t*) ((char*)value + sizeof(uint64_t));
X86_CPU(uc, mycpu)->env.fpregs[regid - UC_X86_REG_FP0].d = cpu_set_fp80(mant, upper);
}
continue;
@@ -676,7 +719,14 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
continue;
}
break;
case UC_X86_REG_XMM0 ... UC_X86_REG_XMM7:
case UC_X86_REG_XMM0:
case UC_X86_REG_XMM1:
case UC_X86_REG_XMM2:
case UC_X86_REG_XMM3:
case UC_X86_REG_XMM4:
case UC_X86_REG_XMM5:
case UC_X86_REG_XMM6:
case UC_X86_REG_XMM7:
{
float64 *src = (float64*)value;
XMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0];
@@ -714,10 +764,21 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
switch(regid) {
default:
break;
case UC_X86_REG_CR0 ... UC_X86_REG_CR4:
case UC_X86_REG_CR0:
case UC_X86_REG_CR1:
case UC_X86_REG_CR2:
case UC_X86_REG_CR3:
case UC_X86_REG_CR4:
X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint32_t *)value;
break;
case UC_X86_REG_DR0 ... UC_X86_REG_DR7:
case UC_X86_REG_DR0:
case UC_X86_REG_DR1:
case UC_X86_REG_DR2:
case UC_X86_REG_DR3:
case UC_X86_REG_DR4:
case UC_X86_REG_DR5:
case UC_X86_REG_DR6:
case UC_X86_REG_DR7:
X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint32_t *)value;
break;
case UC_X86_REG_EFLAGS:
@@ -854,10 +915,21 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
switch(regid) {
default:
break;
case UC_X86_REG_CR0 ... UC_X86_REG_CR4:
case UC_X86_REG_CR0:
case UC_X86_REG_CR1:
case UC_X86_REG_CR2:
case UC_X86_REG_CR3:
case UC_X86_REG_CR4:
X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint64_t *)value;
break;
case UC_X86_REG_DR0 ... UC_X86_REG_DR7:
case UC_X86_REG_DR0:
case UC_X86_REG_DR1:
case UC_X86_REG_DR2:
case UC_X86_REG_DR3:
case UC_X86_REG_DR4:
case UC_X86_REG_DR5:
case UC_X86_REG_DR6:
case UC_X86_REG_DR7:
X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint64_t *)value;
break;
case UC_X86_REG_EFLAGS:
@@ -1133,7 +1205,7 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
return 0;
}
__attribute__ ((visibility ("default")))
DEFAULT_VISIBILITY
int x86_uc_machine_init(struct uc_struct *uc)
{
return machine_initialize(uc);
@@ -1151,7 +1223,7 @@ static bool x86_stop_interrupt(int intno)
void pc_machine_init(struct uc_struct *uc);
__attribute__ ((visibility ("default")))
DEFAULT_VISIBILITY
void x86_uc_init(struct uc_struct* uc)
{
apic_register_types(uc);