This code should now build the x86_x64-softmmu part 2.

qemu/target-arm/arm-semi.c

@@ -21,7 +21,7 @@
 #include <sys/types.h>
 #include <sys/stat.h>
 #include <fcntl.h>
-#include <unistd.h>
+#include "platform.h"
 #include <stdlib.h>
 #include <stdio.h>
 #include <time.h>

qemu/target-arm/translate-a64.c

@@ -20,7 +20,7 @@
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
-#include <inttypes.h>
+#include "platform.h"
 
 #include "cpu.h"
 #include "tcg-op.h"

qemu/target-arm/translate.c

@@ -23,7 +23,7 @@
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
-#include <inttypes.h>
+#include "platform.h"
 
 #include "cpu.h"
 #include "internals.h"

qemu/target-arm/unicorn.h

@@ -13,10 +13,10 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals,
 void arm_reg_reset(struct uc_struct *uc);
 void arm64_reg_reset(struct uc_struct *uc);
 
-__attribute__ ((visibility ("default")))
+DEFAULT_VISIBILITY
 void arm_uc_init(struct uc_struct* uc);
 
-__attribute__ ((visibility ("default")))
+DEFAULT_VISIBILITY
 void arm64_uc_init(struct uc_struct* uc);
 
 extern const int ARM_REGS_STORAGE_SIZE;

qemu/target-arm/unicorn_aarch64.c

@@ -113,7 +113,7 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals,
     return 0;
 }
 
-__attribute__ ((visibility ("default")))
+DEFAULT_VISIBILITY
 void arm64_uc_init(struct uc_struct* uc)
 {
     register_accel_types(uc);