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Updates to Haskell bindings (#667)

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* [haskell] Added uc_context_* support

As per issue #662

* [haskell] Updated bindings for commit 4083b87032

Updated for introduction of UC_HOOK_MEM_READ_AFTER.

* [haskell] Style fixes
This commit is contained in:
Adrian Herrera
2016-10-30 03:51:02 +01:00
committed by Nguyen Anh Quynh
parent 4d5738eeb5
commit 19028f41f6
15 changed files with 594 additions and 410 deletions
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21
bindings/haskell/src/Unicorn/CPU/Arm.chs
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@@ -8,22 +8,25 @@ License : GPL-2
Definitions for the ARM architecture.
-}
module Unicorn.CPU.Arm (
Register(..),
) where
module Unicorn.CPU.Arm
(
Register(..)
) where
import Unicorn.Internal.Core (Reg)
{# context lib="unicorn" #}
{# context lib = "unicorn" #}
#include <unicorn/arm.h>
-- | ARM registers.
{# enum uc_arm_reg as Register
{underscoreToCase}
omit (UC_ARM_REG_INVALID,
UC_ARM_REG_ENDING)
with prefix="UC_ARM_REG_"
deriving (Show, Eq, Bounded) #}
{ underscoreToCase }
omit ( UC_ARM_REG_INVALID
, UC_ARM_REG_ENDING
)
with prefix = "UC_ARM_REG_"
deriving (Show, Eq, Bounded)
#}
instance Reg Register

21
bindings/haskell/src/Unicorn/CPU/Arm64.chs
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@@ -8,22 +8,25 @@ License : GPL-2
Definitions for the ARM64 (ARMv8) architecture.
-}
module Unicorn.CPU.Arm64 (
Register(..),
) where
module Unicorn.CPU.Arm64
(
Register(..)
) where
import Unicorn.Internal.Core (Reg)
{# context lib="unicorn" #}
{# context lib = "unicorn" #}
#include <unicorn/arm64.h>
-- | ARM64 registers.
{# enum uc_arm64_reg as Register
{underscoreToCase}
omit (UC_ARM64_REG_INVALID,
UC_ARM64_REG_ENDING)
with prefix="UC_ARM64_REG_"
deriving (Show, Eq, Bounded) #}
{ underscoreToCase }
omit ( UC_ARM64_REG_INVALID
, UC_ARM64_REG_ENDING
)
with prefix = "UC_ARM64_REG_"
deriving (Show, Eq, Bounded)
#}
instance Reg Register

21
bindings/haskell/src/Unicorn/CPU/M68k.chs
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@@ -8,22 +8,25 @@ License : GPL-2
Definitions for the MK68K architecture.
-}
module Unicorn.CPU.M68k (
Register(..),
) where
module Unicorn.CPU.M68k
(
Register(..)
) where
import Unicorn.Internal.Core (Reg)
{# context lib="unicorn" #}
{# context lib = "unicorn" #}
#include <unicorn/m68k.h>
-- | M68K registers.
{# enum uc_m68k_reg as Register
{underscoreToCase}
omit (UC_M68K_REG_INVALID,
UC_M68K_REG_ENDING)
with prefix="UC_M68K_REG_"
deriving (Show, Eq, Bounded) #}
{ underscoreToCase }
omit ( UC_M68K_REG_INVALID
, UC_M68K_REG_ENDING
)
with prefix = "UC_M68K_REG_"
deriving (Show, Eq, Bounded)
#}
instance Reg Register

86
bindings/haskell/src/Unicorn/CPU/Mips.chs
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@@ -8,54 +8,58 @@ License : GPL-2
Definitions for the MIPS architecture.
-}
module Unicorn.CPU.Mips (
Register(..),
) where
module Unicorn.CPU.Mips
(
Register(..)
) where
import Unicorn.Internal.Core (Reg)
{# context lib="unicorn" #}
{# context lib = "unicorn" #}
#include <unicorn/mips.h>
-- | MIPS registers.
{# enum UC_MIPS_REG as Register
{underscoreToCase,
UC_MIPS_REG_0 as Reg0,
UC_MIPS_REG_1 as Reg1,
UC_MIPS_REG_2 as Reg2,
UC_MIPS_REG_3 as Reg3,
UC_MIPS_REG_4 as Reg4,
UC_MIPS_REG_5 as Reg5,
UC_MIPS_REG_6 as Reg6,
UC_MIPS_REG_7 as Reg7,
UC_MIPS_REG_8 as Reg8,
UC_MIPS_REG_9 as Reg9,
UC_MIPS_REG_10 as Reg10,
UC_MIPS_REG_11 as Reg11,
UC_MIPS_REG_12 as Reg12,
UC_MIPS_REG_13 as Reg13,
UC_MIPS_REG_14 as Reg14,
UC_MIPS_REG_15 as Reg15,
UC_MIPS_REG_16 as Reg16,
UC_MIPS_REG_17 as Reg17,
UC_MIPS_REG_18 as Reg18,
UC_MIPS_REG_19 as Reg19,
UC_MIPS_REG_20 as Reg20,
UC_MIPS_REG_21 as Reg21,
UC_MIPS_REG_22 as Reg22,
UC_MIPS_REG_23 as Reg23,
UC_MIPS_REG_24 as Reg24,
UC_MIPS_REG_25 as Reg25,
UC_MIPS_REG_26 as Reg26,
UC_MIPS_REG_27 as Reg27,
UC_MIPS_REG_28 as Reg28,
UC_MIPS_REG_29 as Reg29,
UC_MIPS_REG_30 as Reg30,
UC_MIPS_REG_31 as Reg31}
omit (UC_MIPS_REG_INVALID,
UC_MIPS_REG_ENDING)
with prefix="UC_MIPS_REG_"
deriving (Show, Eq, Bounded) #}
{ underscoreToCase
, UC_MIPS_REG_0 as Reg0g
, UC_MIPS_REG_1 as Reg1g
, UC_MIPS_REG_2 as Reg2g
, UC_MIPS_REG_3 as Reg3g
, UC_MIPS_REG_4 as Reg4g
, UC_MIPS_REG_5 as Reg5g
, UC_MIPS_REG_6 as Reg6g
, UC_MIPS_REG_7 as Reg7g
, UC_MIPS_REG_8 as Reg8g
, UC_MIPS_REG_9 as Reg9g
, UC_MIPS_REG_10 as Reg10g
, UC_MIPS_REG_11 as Reg11g
, UC_MIPS_REG_12 as Reg12g
, UC_MIPS_REG_13 as Reg13g
, UC_MIPS_REG_14 as Reg14g
, UC_MIPS_REG_15 as Reg15g
, UC_MIPS_REG_16 as Reg16g
, UC_MIPS_REG_17 as Reg17g
, UC_MIPS_REG_18 as Reg18g
, UC_MIPS_REG_19 as Reg19g
, UC_MIPS_REG_20 as Reg20g
, UC_MIPS_REG_21 as Reg21g
, UC_MIPS_REG_22 as Reg22g
, UC_MIPS_REG_23 as Reg23g
, UC_MIPS_REG_24 as Reg24g
, UC_MIPS_REG_25 as Reg25g
, UC_MIPS_REG_26 as Reg26g
, UC_MIPS_REG_27 as Reg27g
, UC_MIPS_REG_28 as Reg28g
, UC_MIPS_REG_29 as Reg29g
, UC_MIPS_REG_30 as Reg30g
, UC_MIPS_REG_31 as Reg31
}
omit ( UC_MIPS_REG_INVALID
, UC_MIPS_REG_ENDING
)
with prefix = "UC_MIPS_REG_"
deriving (Show, Eq, Bounded)
#}
instance Reg Register

21
bindings/haskell/src/Unicorn/CPU/Sparc.chs
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@@ -8,22 +8,25 @@ License : GPL-2
Definitions for the SPARC architecture.
-}
module Unicorn.CPU.Sparc (
Register(..),
) where
module Unicorn.CPU.Sparc
(
Register(..)
) where
import Unicorn.Internal.Core (Reg)
{# context lib="unicorn" #}
{# context lib = "unicorn" #}
#include <unicorn/sparc.h>
-- | SPARC registers.
{# enum uc_sparc_reg as Register
{underscoreToCase}
omit (UC_SPARC_REG_INVALID,
UC_SPARC_REG_ENDING)
with prefix="UC_SPARC_REG_"
deriving (Show, Eq, Bounded) #}
{ underscoreToCase }
omit (UC_SPARC_REG_INVALID
, UC_SPARC_REG_ENDING
)
with prefix = "UC_SPARC_REG_"
deriving (Show, Eq, Bounded)
#}
instance Reg Register

49
bindings/haskell/src/Unicorn/CPU/X86.chs
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@@ -8,11 +8,12 @@ License : GPL-2
Definitions for the X86 architecture.
-}
module Unicorn.CPU.X86 (
Mmr(..),
Register(..),
Instruction(..),
) where
module Unicorn.CPU.X86
(
Mmr(..)
, Register(..)
, Instruction(..)
) where
import Control.Applicative
import Data.Word
@@ -20,18 +21,18 @@ import Foreign
import Unicorn.Internal.Core (Reg)
{# context lib="unicorn" #}
{# context lib = "unicorn" #}
#include <unicorn/x86.h>
-- | Memory-managemen Register for instructions IDTR, GDTR, LDTR, TR.
-- Borrow from SegmentCache in qemu/target-i386/cpu.h
data Mmr = Mmr {
mmrSelector :: Word16, -- ^ Not used by GDTR and IDTR
mmrBase :: Word64, -- ^ Handle 32 or 64 bit CPUs
mmrLimit :: Word32,
mmrFlags :: Word32 -- ^ Not used by GDTR and IDTR
}
data Mmr = Mmr
{ mmrSelector :: Word16 -- ^ Not used by GDTR and IDTR
, mmrBase :: Word64 -- ^ Handle 32 or 64 bit CPUs
, mmrLimit :: Word32
, mmrFlags :: Word32 -- ^ Not used by GDTR and IDTR
}
instance Storable Mmr where
sizeOf _ = {# sizeof uc_x86_mmr #}
@@ -48,18 +49,22 @@ instance Storable Mmr where
-- | X86 registers.
{# enum uc_x86_reg as Register
{underscoreToCase}
omit (UC_X86_REG_INVALID,
UC_X86_REG_ENDING)
with prefix="UC_X86_REG_"
deriving (Show, Eq, Bounded) #}
{ underscoreToCase }
omit ( UC_X86_REG_INVALID
, UC_X86_REG_ENDING
)
with prefix = "UC_X86_REG_"
deriving (Show, Eq, Bounded)
#}
instance Reg Register
-- | X86 instructions.
{# enum uc_x86_insn as Instruction
{underscoreToCase}
omit (UC_X86_INS_INVALID,
UC_X86_INS_ENDING)
with prefix="UC_X86_INS_"
deriving (Show, Eq, Bounded) #}
{ underscoreToCase }
omit ( UC_X86_INS_INVALID
, UC_X86_INS_ENDING
)
with prefix = "UC_X86_INS_"
deriving (Show, Eq, Bounded)
#}