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Also initialize CR4 for UC_MODE_32

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mio
2025-02-18 10:47:35 +08:00
parent 1dae6bb774
commit 0f6ec4ca9d
1 changed files with 22 additions and 11 deletions
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23
qemu/target/i386/unicorn.c
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@@ -160,14 +160,24 @@ static void reg_reset(struct uc_struct *uc)
break; break;
case UC_MODE_32: case UC_MODE_32:
env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_OSFXSR_MASK; env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_OSFXSR_MASK;
cpu_x86_update_cr0(env, CR0_PE_MASK); // protected mode
break; break;
case UC_MODE_64: case UC_MODE_64:
env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK |
HF_LMA_MASK | HF_OSFXSR_MASK; HF_LMA_MASK | HF_OSFXSR_MASK;
env->hflags &= ~(HF_ADDSEG_MASK); env->hflags &= ~(HF_ADDSEG_MASK);
env->efer |= MSR_EFER_LMA | MSR_EFER_LME; // extended mode activated env->efer |= MSR_EFER_LMA | MSR_EFER_LME; // extended mode activated
cpu_x86_update_cr0(env, CR0_PE_MASK); // protected mode
/* If we are operating in 64bit mode then add the Long Mode flag
* to the CPUID feature flag
*/
env->features[FEAT_8000_0001_EDX] |= CPUID_EXT2_LM;
break;
}
// CR initialization
switch (uc->mode) {
case UC_MODE_32:
case UC_MODE_64: {
uint32_t cr4 = 0; uint32_t cr4 = 0;
if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
@@ -176,11 +186,12 @@ static void reg_reset(struct uc_struct *uc)
if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
cr4 |= CR4_FSGSBASE_MASK; cr4 |= CR4_FSGSBASE_MASK;
} }
cpu_x86_update_cr0(env, CR0_PE_MASK); // protected mode
cpu_x86_update_cr4(env, cr4); cpu_x86_update_cr4(env, cr4);
/* If we are operating in 64bit mode then add the Long Mode flag break;
* to the CPUID feature flag }
*/ default:
env->features[FEAT_8000_0001_EDX] |= CPUID_EXT2_LM;
break; break;
} }
} }