uc_ctl proposal (#1473)
* Add uc_ctl * Add comments * Slightly changed for bindings generation * Generate bindings
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@@ -7,6 +7,16 @@ open System
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[<AutoOpen>]
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module Riscv =
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let UC_CPU_RISCV32_ANY = 0
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let UC_CPU_RISCV32_BASE32 = 1
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let UC_CPU_RISCV32_SIFIVE_E31 = 2
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let UC_CPU_RISCV32_SIFIVE_U34 = 3
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let UC_CPU_RISCV64_ANY = 0
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let UC_CPU_RISCV64_BASE64 = 1
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let UC_CPU_RISCV64_SIFIVE_E51 = 2
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let UC_CPU_RISCV64_SIFIVE_U54 = 3
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// RISCV registers
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let UC_RISCV_REG_INVALID = 0
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