From d96083d4d1ce128209ed1d93c9c780287db4d04e Mon Sep 17 00:00:00 2001
From: Bet4 <0xbet4@gmail.com>
Date: Sat, 19 Feb 2022 21:20:41 +0800
Subject: [PATCH] Fix pc after ppc sc inst

---
 qemu/accel/tcg/cpu-exec.c |  4 ++++
 tests/unit/test_ppc.c     | 27 +++++++++++++++++++++++++++
 2 files changed, 31 insertions(+)

diff --git a/qemu/accel/tcg/cpu-exec.c b/qemu/accel/tcg/cpu-exec.c
index 6c228f94..d4e90f68 100644
--- a/qemu/accel/tcg/cpu-exec.c
+++ b/qemu/accel/tcg/cpu-exec.c
@@ -386,6 +386,10 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
 #if defined(TARGET_RISCV)
         CPURISCVState *env = &(RISCV_CPU(uc->cpu)->env);
         env->pc += 4;
+#endif
+#if defined(TARGET_PPC)
+        CPUPPCState *env = &(POWERPC_CPU(uc->cpu)->env);
+        env->nip += 4;
 #endif
         // Unicorn: call registered interrupt callbacks
         catched = false;
diff --git a/tests/unit/test_ppc.c b/tests/unit/test_ppc.c
index 21ba64fa..835d9857 100644
--- a/tests/unit/test_ppc.c
+++ b/tests/unit/test_ppc.c
@@ -63,6 +63,33 @@ static void test_ppc32_fadd()
     OK(uc_close(uc));
 }
 
+static void test_ppc32_sc_cb(uc_engine *uc, uint32_t intno, void *data)
+{
+    uc_emu_stop(uc);
+    return;
+}
+
+static void test_ppc32_sc()
+{
+    uc_engine *uc;
+    char code[] = "\x44\x00\x00\x02"; // sc
+    uint32_t r_pc;
+    uc_hook h;
+
+    uc_common_setup(&uc, UC_ARCH_PPC, UC_MODE_32 | UC_MODE_BIG_ENDIAN, code,
+                    sizeof(code) - 1);
+
+    OK(uc_hook_add(uc, &h, UC_HOOK_INTR, test_ppc32_sc_cb, NULL, 1, 0));
+    OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
+
+    OK(uc_reg_read(uc, UC_PPC_REG_PC, &r_pc));
+
+    TEST_CHECK(r_pc == code_start + 4);
+
+    OK(uc_close(uc));
+}
+
 TEST_LIST = {{"test_ppc32_add", test_ppc32_add},
              {"test_ppc32_fadd", test_ppc32_fadd},
+             {"test_ppc32_sc", test_ppc32_sc},
              {NULL, NULL}};
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